Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (65 commits)
  ARM: 6826/1: Merge v6 and v7 DEBUG_LL DCC support
  ARM: 6838/1: etm: fix section mismatch warning
  ARM: 6837/1: remove unused pci_fixup_prpmc1100
  ARM: 6836/1: kprobes/fix emulation of LDR/STR instruction when Rn == PC
  Fix the broken build for Marvell Dove platform.
  ARM: 6835/1: perf: ensure overflows aren't missed due to IRQ latency
  ARM: 6834/1: perf: reset counters on all CPUs during initialisation
  ARM: 6833/1: perf: add required isbs() to ARMv7 backend
  ARM: 6825/1: kernel/sleep.S: fix Thumb2 compilation issues
  ARM: 6807/1: realview: Fix secondary GIC initialisation for EB with MPCore tile
  arm: mach-mx3: pcm043: add write-protect and card-detect for SD1
  eukrea_mbimxsd51: add SD Card detect
  eukrea_mbimxsd25-baseboard: add SD card detect
  mx3/eukrea_mbimxsd-baseboard: add SD card detect support
  mx3/eukrea_mbimxsd-baseboard: fix gpio request
  ARM: mxs/mx28evk: add mmc device
  ARM: mxs/mx23evk: add mmc device
  ARM: mxs: dynamically allocate mmc device
  ARM: mx51_efika: update platform data for new mfd changes
  mx2/iomux: Set direction for CSPI2 pins
  ...

1 files changed, 25 insertions, 8 deletions

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 22e194eb853..69cfee0fe00 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -79,6 +79,7 @@ struct arm_pmu {
 	void		(*write_counter)(int idx, u32 val);
 	void		(*start)(void);
 	void		(*stop)(void);
+	void		(*reset)(void *);
 	const unsigned	(*cache_map)[PERF_COUNT_HW_CACHE_MAX]
 				    [PERF_COUNT_HW_CACHE_OP_MAX]
 				    [PERF_COUNT_HW_CACHE_RESULT_MAX];
@@ -204,11 +205,9 @@ armpmu_event_set_period(struct perf_event *event,
 static u64
 armpmu_event_update(struct perf_event *event,
 		    struct hw_perf_event *hwc,
-		    int idx)
+		    int idx, int overflow)
 {
-	int shift = 64 - 32;
-	s64 prev_raw_count, new_raw_count;
-	u64 delta;
+	u64 delta, prev_raw_count, new_raw_count;
 
 again:
 	prev_raw_count = local64_read(&hwc->prev_count);
@@ -218,8 +217,13 @@ again:
 			     new_raw_count) != prev_raw_count)
 		goto again;
 
-	delta = (new_raw_count << shift) - (prev_raw_count << shift);
-	delta >>= shift;
+	new_raw_count &= armpmu->max_period;
+	prev_raw_count &= armpmu->max_period;
+
+	if (overflow)
+		delta = armpmu->max_period - prev_raw_count + new_raw_count;
+	else
+		delta = new_raw_count - prev_raw_count;
 
 	local64_add(delta, &event->count);
 	local64_sub(delta, &hwc->period_left);
@@ -236,7 +240,7 @@ armpmu_read(struct perf_event *event)
 	if (hwc->idx < 0)
 		return;
 
-	armpmu_event_update(event, hwc, hwc->idx);
+	armpmu_event_update(event, hwc, hwc->idx, 0);
 }
 
 static void
@@ -254,7 +258,7 @@ armpmu_stop(struct perf_event *event, int flags)
 	if (!(hwc->state & PERF_HES_STOPPED)) {
 		armpmu->disable(hwc, hwc->idx);
 		barrier(); /* why? */
-		armpmu_event_update(event, hwc, hwc->idx);
+		armpmu_event_update(event, hwc, hwc->idx, 0);
 		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 	}
 }
@@ -624,6 +628,19 @@ static struct pmu pmu = {
 #include "perf_event_v6.c"
 #include "perf_event_v7.c"
 
+/*
+ * Ensure the PMU has sane values out of reset.
+ * This requires SMP to be available, so exists as a separate initcall.
+ */
+static int __init
+armpmu_reset(void)
+{
+	if (armpmu && armpmu->reset)
+		return on_each_cpu(armpmu->reset, NULL, 1);
+	return 0;
+}
+arch_initcall(armpmu_reset);
+
 static int __init
 init_hw_perf_events(void)
 {