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authorIngo Molnar <mingo@elte.hu>2009-03-06 11:47:52 +0100
committerIngo Molnar <mingo@elte.hu>2009-03-06 11:47:52 +0100
commit7fc07d84108d54c5b94625c0e168f31b2d66976e (patch)
treebebcbcae186108a815de0c1b90e25b1a5fa3852c /arch/arm/kernel/setup.c
parentb67802ea8061393f7bd2d4db934646e76096027c (diff)
parent8a0be9ef8225638d26b455788f988c8f84ce9e75 (diff)
Merge branch 'sched/core' into sched/cleanups
Diffstat (limited to 'arch/arm/kernel/setup.c')
-rw-r--r--arch/arm/kernel/setup.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 7049815d66d..68d6494c038 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -233,12 +233,13 @@ static void __init cacheid_init(void)
unsigned int cachetype = read_cpuid_cachetype();
unsigned int arch = cpu_architecture();
- if (arch >= CPU_ARCH_ARMv7) {
- cacheid = CACHEID_VIPT_NONALIASING;
- if ((cachetype & (3 << 14)) == 1 << 14)
- cacheid |= CACHEID_ASID_TAGGED;
- } else if (arch >= CPU_ARCH_ARMv6) {
- if (cachetype & (1 << 23))
+ if (arch >= CPU_ARCH_ARMv6) {
+ if ((cachetype & (7 << 29)) == 4 << 29) {
+ /* ARMv7 register format */
+ cacheid = CACHEID_VIPT_NONALIASING;
+ if ((cachetype & (3 << 14)) == 1 << 14)
+ cacheid |= CACHEID_ASID_TAGGED;
+ } else if (cachetype & (1 << 23))
cacheid = CACHEID_VIPT_ALIASING;
else
cacheid = CACHEID_VIPT_NONALIASING;