diff options
| author | Will Deacon <will.deacon@arm.com> | 2011-11-22 17:30:28 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2011-12-08 10:30:38 +0000 |
| commit | d675d0bc47f28c5414fbbe17fcc801f69c45b960 (patch) | |
| tree | 78d7b2c43650d6af96caac9e631409cf15c8f25a /arch/arm/kernel/sleep.S | |
| parent | 8d2cd3a38fd663bd341507f5ac29002ffd81d986 (diff) | |
ARM: LPAE: add ISBs around MMU enabling code
Before we enable the MMU, we must ensure that the TTBR registers contain
sane values. After the MMU has been enabled, we jump to the *virtual*
address of the following function, so we also need to ensure that the
SCTLR write has taken effect.
This patch adds ISB instructions around the SCTLR write to ensure the
visibility of the above.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/kernel/sleep.S')
| -rw-r--r-- | arch/arm/kernel/sleep.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index 9e64231c8cf..1f268bda455 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -57,8 +57,10 @@ ENDPROC(cpu_suspend_abort) .pushsection .idmap.text,"ax" ENTRY(cpu_resume_mmu) ldr r3, =cpu_resume_after_mmu + instr_sync mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc mrc p15, 0, r0, c0, c0, 0 @ read id reg + instr_sync mov r0, r0 mov r0, r0 mov pc, r3 @ jump to virtual address |