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authorLinus Torvalds <torvalds@linux-foundation.org>2012-01-09 14:21:03 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2012-01-09 14:21:03 -0800
commitacc952c1f373bf3f66cc7a10680eee1762bed40b (patch)
treede1135ffe304f4d8e53d282e5bb1bde5db04e0ae /arch/arm/mach-at91/include/mach/at91sam9_smc.h
parent57e964e1ae9bd4f699ae1074430bcf81a9a11377 (diff)
parent40ba95fdf158713377d47736b1b3a9d75f4f2515 (diff)
Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Cleanups on various subarchitectures Cleanup patches for various ARM platforms and some of their associated drivers, the bulk of these is for mach-91. Arnd ended up pulling in the restart branch from Russell in order to fix up some simple but annoying merge conflicts. * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (44 commits) arm/at91: fix build of stamp9g20 ARM: u300: delete memory.h MAINTAINERS: add maintainer entry for Picochip picoxcell ARM: picoxcell: move io mappings to common.c ARM: picoxcell: don't reserve irq_descs ARM: picoxcell: remove mach/memory.h ARM: at91: delete the pcontrol_g20_defconfig arm/tegra: Remove code that's ifndef CONFIG_ARM_GIC arm/tegra: remove unused defines arm/tegra: fix variable formatting in makefile ARM: davinci: vpif: move code to driver core header from platform ARM: at91/gpio: fix display of number of irq setuped ARM: at91/gpio: drop PIN_BASE ARM: at91/udc: use gpio_is_valid to check the gpio ARM: at91/ohci: use gpio_is_valid to check the gpio ARM: at91/nand: use gpio_is_valid to check the gpio ARM: at91/mmc: use gpio_is_valid to check the gpio ARM: at91/ide: use gpio_is_valid to check the gpio ARM: at91/pata: use gpio_is_valid to check the gpio ARM: at91/soc: use gpio_is_valid to check the gpio ...
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam9_smc.h')
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_smc.h17
1 files changed, 6 insertions, 11 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index 57de6207e57..eb18a70fa64 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -16,7 +16,9 @@
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
-#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#include <mach/cpu.h>
+
+#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
@@ -26,7 +28,7 @@
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
-#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
@@ -36,13 +38,13 @@
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
-#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
@@ -66,11 +68,4 @@
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
-#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
-
#endif