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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-02-13 14:58:30 +0800
committerNicolas Ferre <nicolas.ferre@atmel.com>2012-04-17 14:46:43 +0200
commitefd09165aa554f84a42565d5ae6a1af58b06a97a (patch)
tree3ca981db0ec5b7882f8e07f2ef204e97ea1b63f9 /arch/arm/mach-at91/pm.h
parent7eb1dbb3beb982a7d72514abff96ebc08a22e5cd (diff)
ARM: at91: pm select memory controler at runtime
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> [nicolas.ferre@atmel.com: add cpuidle modification] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/pm.h')
-rw-r--r--arch/arm/mach-at91/pm.h13
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 89f56f3a802..1b4865e7571 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -12,7 +12,6 @@
#define __ARCH_ARM_MACH_AT91_PM
#include <mach/at91_ramc.h>
-#ifdef CONFIG_ARCH_AT91RM9200
#include <mach/at91rm9200_sdramc.h>
/*
@@ -43,10 +42,6 @@ static inline void at91rm9200_standby(void)
"r" (lpr));
}
-#define at91_standby at91rm9200_standby
-
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
-
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
* remember.
*/
@@ -75,10 +70,6 @@ static inline void at91sam9g45_standby(void)
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
}
-#define at91_standby at91sam9g45_standby
-
-#else
-
#ifdef CONFIG_ARCH_AT91SAM9263
/*
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
@@ -102,8 +93,4 @@ static inline void at91sam9_standby(void)
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
}
-#define at91_standby at91sam9_standby
-
-#endif
-
#endif