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| author | Nicolas Ferre <nicolas.ferre@atmel.com> | 2010-10-22 18:55:39 +0200 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2010-10-26 11:32:48 +0200 |
| commit | a2a571b74a3881963d8d09deb272d13afe5b49e3 (patch) | |
| tree | 491cf5ff56293287906f9cfec785345f24cd2180 /arch/arm/mach-at91/pm_slowclock.S | |
| parent | 8aeeda822fbfe7da2d4ea391a9757e9532796598 (diff) | |
AT91: pm: make sure that r0 is 0 when dealing with cache operations
When using CP15 cache operations (c7), we make sure that Rd (r0)
is actually 0 as ARM 926 TRM is saying.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/pm_slowclock.S')
| -rw-r--r-- | arch/arm/mach-at91/pm_slowclock.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index b6b00a1f612..f7922a43617 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -124,6 +124,7 @@ ENTRY(at91_slow_clock) ldr r5, .at91_va_base_ramc1 /* Drain write buffer */ + mov r0, #0 mcr p15, 0, r0, c7, c10, 4 #ifdef CONFIG_ARCH_AT91RM9200 |