diff options
| author | Sekhar Nori <nsekhar@ti.com> | 2010-07-20 16:46:51 +0530 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-09-24 07:40:25 -0700 |
| commit | b987c4b2c9c9db2393f4c089e63d1734301214e5 (patch) | |
| tree | 446b9ae602d8669e9e03107b976c9a88040b84ca /arch/arm/mach-davinci/da850.c | |
| parent | 30a2c5d2f0134df6175af26ce554aacaee304280 (diff) | |
davinci: am18x/da850/omap-l138: keep async clock constant with cpufreq
Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF
timing to remain valid even as the PLL0 output is changed by cpufreq
driver to save power.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/da850.c')
| -rw-r--r-- | arch/arm/mach-davinci/da850.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 6932d804556..5af7cfb1447 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -86,6 +86,8 @@ static struct clk pll0_sysclk3 = { .parent = &pll0_clk, .flags = CLK_PLL, .div_reg = PLLDIV3, + .set_rate = davinci_set_sysclk_rate, + .maxrate = 100000000, }; static struct clk pll0_sysclk4 = { @@ -929,10 +931,16 @@ static struct platform_device da850_cpufreq_device = { .dev = { .platform_data = &cpufreq_info, }, + .id = -1, }; -int __init da850_register_cpufreq(void) +int __init da850_register_cpufreq(char *async_clk) { + /* cpufreq driver can help keep an "async" clock constant */ + if (async_clk) + clk_add_alias("async", da850_cpufreq_device.name, + async_clk, NULL); + return platform_device_register(&da850_cpufreq_device); } |