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authorMark A. Greer <mgreer@mvista.com>2009-04-15 12:40:21 -0700
committerKevin Hilman <khilman@deeprootsystems.com>2009-05-26 08:20:31 -0700
commit951d6f6d703110790256abfce03ced117d2dcc6b (patch)
tree598b30a93ff618f56579d2c1218088bd908e5125 /arch/arm/mach-davinci/time.c
parentf64691b3ab795268072e76ddb89290b6277cdf33 (diff)
davinci: Add watchdog base address flexibility
The watchdog code currently hardcodes the base address of the timer its using. To support new SoCs, make it support timers at any address. Use the soc_info structure to do this. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/time.c')
-rw-r--r--arch/arm/mach-davinci/time.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index faafb897f4b..f80ae25a52e 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -35,8 +35,6 @@
static struct clock_event_device clockevent_davinci;
static unsigned int davinci_clock_tick_rate;
-#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
-
/*
* This driver configures the 2 64-bit count-up timers as 4 independent
* 32-bit count-up timers used as follows:
@@ -343,7 +341,8 @@ struct sys_timer davinci_timer = {
void davinci_watchdog_reset(void)
{
u32 tgcr, wdtcr;
- void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
+ struct davinci_soc_info *soc_info = &davinci_soc_info;
+ void __iomem *base = soc_info->wdt_base;
struct clk *wd_clk;
wd_clk = clk_get(&davinci_wdt_device.dev, NULL);