summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-ebsa110/include/mach/system.h
diff options
context:
space:
mode:
authorIngo Molnar <mingo@elte.hu>2008-10-02 10:21:26 +0200
committerIngo Molnar <mingo@elte.hu>2008-10-02 10:21:26 +0200
commitd6d5aeb661fc14655c417f3582ae7ec52985d2a8 (patch)
tree5e168da05cb28d10b5accc74718428cfd5527201 /arch/arm/mach-ebsa110/include/mach/system.h
parent7e6e178ab1548c8d894a77593e757acf4510b8ba (diff)
parent94aca1dac6f6d21f4b07e4864baf7768cabcc6e7 (diff)
Merge commit 'v2.6.27-rc8' into genirq
Diffstat (limited to 'arch/arm/mach-ebsa110/include/mach/system.h')
-rw-r--r--arch/arm/mach-ebsa110/include/mach/system.h39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h
new file mode 100644
index 00000000000..350a028997e
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/system.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-ebsa110/include/mach/system.h
+ *
+ * Copyright (C) 1996-2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+/*
+ * EBSA110 idling methodology:
+ *
+ * We can not execute the "wait for interrupt" instruction since that
+ * will stop our MCLK signal (which provides the clock for the glue
+ * logic, and therefore the timer interrupt).
+ *
+ * Instead, we spin, polling the IRQ_STAT register for the occurrence
+ * of any interrupt with core clock down to the memory clock.
+ */
+static inline void arch_idle(void)
+{
+ const char *irq_stat = (char *)0xff000000;
+
+ /* disable clock switching */
+ asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
+
+ /* wait for an interrupt to occur */
+ while (!*irq_stat);
+
+ /* enable clock switching */
+ asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
+}
+
+#define arch_reset(mode) cpu_reset(0x80000000)
+
+#endif