diff options
| author | Kisoo Yu <ksoo.yu@samsung.com> | 2012-04-24 14:54:15 -0700 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-05-16 07:03:41 +0900 |
| commit | 57b317f912b3f4b05c834818c73d7c8ea22642f7 (patch) | |
| tree | 9963b419762b3bbe9a30544c9543edb199df5cde /arch/arm/mach-exynos/include/mach | |
| parent | f10590c9836c9fc595d1dafff965b280029d4f16 (diff) | |
ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250.
The clock options are a fixed divided by 2 clock and the output of the
PLL itself. Add support for these new clock instances.
Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/include/mach')
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-clock.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index dba83e91f0f..b78b5f3ad9c 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -322,6 +322,8 @@ #define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) #define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) +#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24) + #define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) |