diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-01-07 12:44:37 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-01-07 20:40:51 +0000 |
| commit | b001befe58691ef3627458cd814e8cee7f845c5f (patch) | |
| tree | 1083f1a1cd3feeceeac4b395534df0ff032fdbc8 /arch/arm/mach-exynos/platsmp.c | |
| parent | 31b2a868451d630bacfdeddc626371b3f9d9a01c (diff) | |
| parent | 928a11ba36f999436915ea2b1eadf54301f93059 (diff) | |
Merge branch 'samsung/dt' into next/dt
* samsung/dt: (3 commit)
Merge branch 'depends/rmk/for-linus' into samsung/dt
Merge branch 'depends/rmk/restart' into next/cleanup
Merge branch 'next/cleanup' into samsung/dt
Conflicts:
arch/arm/mach-tegra/board-dt.c
arch/arm/mach-tegra/include/mach/entry-macro.S
The latest version of the samsung/dt branch resolves
all sorts of conflicts with the latest upstream, no functional
changes that are not already there.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-exynos/platsmp.c')
| -rw-r--r-- | arch/arm/mach-exynos/platsmp.c | 28 |
1 files changed, 1 insertions, 27 deletions
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 69ffb2fb387..60bc45e3e70 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -32,7 +32,6 @@ #include <plat/cpu.h> -extern unsigned int gic_bank_offset; extern void exynos4_secondary_startup(void); #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ @@ -65,31 +64,6 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(boot_lock); -static void __cpuinit exynos4_gic_secondary_init(void) -{ - void __iomem *dist_base = S5P_VA_GIC_DIST + - (gic_bank_offset * smp_processor_id()); - void __iomem *cpu_base = S5P_VA_GIC_CPU + - (gic_bank_offset * smp_processor_id()); - int i; - - /* - * Deal with the banked PPI and SGI interrupts - disable all - * PPI interrupts, ensure all SGI interrupts are enabled. - */ - __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); - __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); - - /* - * Set priority on PPI and SGI interrupts - */ - for (i = 0; i < 32; i += 4) - __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); - - __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK); - __raw_writel(1, cpu_base + GIC_CPU_CTRL); -} - void __cpuinit platform_secondary_init(unsigned int cpu) { /* @@ -97,7 +71,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - exynos4_gic_secondary_init(); + gic_secondary_init(0); /* * let the primary processor know we're out of the |