diff options
author | Dave Airlie <airlied@redhat.com> | 2011-12-20 14:43:53 +0000 |
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committer | Dave Airlie <airlied@redhat.com> | 2011-12-20 14:43:53 +0000 |
commit | 1fbe6f625f69e48c4001051dc1431afc704acfaa (patch) | |
tree | 826b741201a2e09a627ed350c6ff36935f5cff79 /arch/arm/mach-imx/clock-imx6q.c | |
parent | 0cecdd818cd79d092e36e70dfe3a71f2878d6b96 (diff) | |
parent | 384703b8e6cd4c8ef08512e596024e028c91c339 (diff) |
Merge tag 'v3.2-rc6' of /home/airlied/devel/kernel/linux-2.6 into drm-core-next
Merge in the upstream tree to bring in the mainline fixes.
Conflicts:
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
drivers/gpu/drm/nouveau/nouveau_sgdma.c
Diffstat (limited to 'arch/arm/mach-imx/clock-imx6q.c')
-rw-r--r-- | arch/arm/mach-imx/clock-imx6q.c | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index e0b926dfece..039a7abb165 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c @@ -1139,7 +1139,7 @@ static int _clk_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; max_div = ((d->bm_pred >> d->bp_pred) + 1) * - ((d->bm_pred >> d->bp_pred) + 1); + ((d->bm_podf >> d->bp_podf) + 1); div = parent_rate / rate; if (div == 0) @@ -1953,14 +1953,17 @@ static struct map_desc imx6q_clock_desc[] = { imx_map_entry(MX6Q, ANATOP, MT_DEVICE), }; +void __init imx6q_clock_map_io(void) +{ + iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc)); +} + int __init mx6q_clocks_init(void) { struct device_node *np; void __iomem *base; int i, irq; - iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc)); - /* retrieve the freqency of fixed clocks from device tree */ for_each_compatible_node(np, NULL, "fixed-clock") { u32 rate; @@ -2002,6 +2005,21 @@ int __init mx6q_clocks_init(void) clk_set_rate(&asrc_serial_clk, 1500000); clk_set_rate(&enfc_clk, 11000000); + /* + * Before pinctrl API is available, we have to rely on the pad + * configuration set up by bootloader. For usdhc example here, + * u-boot sets up the pads for 49.5 MHz case, and we have to lower + * the usdhc clock from 198 to 49.5 MHz to match the pad configuration. + * + * FIXME: This is should be removed after pinctrl API is available. + * At that time, usdhc driver can call pinctrl API to change pad + * configuration dynamically per different usdhc clock settings. + */ + clk_set_rate(&usdhc1_clk, 49500000); + clk_set_rate(&usdhc2_clk, 49500000); + clk_set_rate(&usdhc3_clk, 49500000); + clk_set_rate(&usdhc4_clk, 49500000); + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); base = of_iomap(np, 0); WARN_ON(!base); |