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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-06 16:50:35 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-06 16:50:35 -0800 |
| commit | 3c0cb7c31c206aaedb967e44b98442bbeb17a6c4 (patch) | |
| tree | 3ecba45d7ffae4fba4a5aafaef4af5b0b1105bde /arch/arm/mach-imx/cpu-imx27.c | |
| parent | f70f5b9dc74ca7d0a64c4ead3fb28da09dc1b234 (diff) | |
| parent | 404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34 (diff) | |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (416 commits)
ARM: DMA: add support for DMA debugging
ARM: PL011: add DMA burst threshold support for ST variants
ARM: PL011: Add support for transmit DMA
ARM: PL011: Ensure IRQs are disabled in UART interrupt handler
ARM: PL011: Separate hardware FIFO size from TTY FIFO size
ARM: PL011: Allow better handling of vendor data
ARM: PL011: Ensure error flags are clear at startup
ARM: PL011: include revision number in boot-time port printk
ARM: vexpress: add sched_clock() for Versatile Express
ARM i.MX53: Make MX53 EVK bootable
ARM i.MX53: Some bug fix about MX53 MSL code
ARM: 6607/1: sa1100: Update platform device registration
ARM: 6606/1: sa1100: Fix platform device registration
ARM i.MX51: rename IPU irqs
ARM i.MX51: Add ipu clock support
ARM: imx/mx27_3ds: Add PMIC support
ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn()
mx51: fix usb clock support
MX51: Add support for usb host 2
arch/arm/plat-mxc/ehci.c: fix errors/typos
...
Diffstat (limited to 'arch/arm/mach-imx/cpu-imx27.c')
| -rw-r--r-- | arch/arm/mach-imx/cpu-imx27.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index d8d3b2d84dc..3b117be37bd 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c @@ -42,7 +42,19 @@ static void query_silicon_parameter(void) val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID)); - cpu_silicon_rev = (int)(val >> 28); + switch (val >> 28) { + case 0: + cpu_silicon_rev = IMX_CHIP_REVISION_1_0; + break; + case 1: + cpu_silicon_rev = IMX_CHIP_REVISION_2_0; + break; + case 2: + cpu_silicon_rev = IMX_CHIP_REVISION_2_1; + break; + default: + cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN; + } cpu_partnumber = (int)((val >> 12) & 0xFFFF); } |