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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-05-23 19:28:04 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-05-23 19:28:04 +0100
commit9a55d9752d8abfc62f1ab05ccc790d22a0c8e7c0 (patch)
tree894bb6a3fb409c6ac5f0374f5a1f656918bc35cd /arch/arm/mach-imx/cpu-imx31.c
parentec19628d72cff8f80220b7cedba089074ac6a599 (diff)
parentdc7ad3b3d5f1cd0a0d16c05dd3ad3898979d261e (diff)
Merge branch 'devel-stable' into for-linus
Conflicts: arch/arm/Kconfig arch/arm/mach-ns9xxx/include/mach/uncompress.h
Diffstat (limited to 'arch/arm/mach-imx/cpu-imx31.c')
-rw-r--r--arch/arm/mach-imx/cpu-imx31.c57
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
new file mode 100644
index 00000000000..a3780700a88
--- /dev/null
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -0,0 +1,57 @@
+/*
+ * MX31 CPU type detection
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/iim.h>
+
+unsigned int mx31_cpu_rev;
+EXPORT_SYMBOL(mx31_cpu_rev);
+
+static struct {
+ u8 srev;
+ const char *name;
+ const char *v;
+ unsigned int rev;
+} mx31_cpu_type[] __initdata = {
+ { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
+ { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
+ { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
+ { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
+ { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
+};
+
+void __init mx31_read_cpu_rev(void)
+{
+ u32 i, srev;
+
+ /* read SREV register from IIM module */
+ srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
+
+ for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+ if (srev == mx31_cpu_type[i].srev) {
+ printk(KERN_INFO
+ "CPU identified as %s, silicon rev %s\n",
+ mx31_cpu_type[i].name, mx31_cpu_type[i].v);
+
+ mx31_cpu_rev = mx31_cpu_type[i].rev;
+ return;
+ }
+
+ mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+
+ printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
+}