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authorShawn Guo <shawn.guo@linaro.org>2011-09-06 14:39:44 +0800
committerArnd Bergmann <arnd@arndb.de>2011-10-31 14:26:23 +0100
commit9fbbe6890c88aa332efe61d5894108dd8b932530 (patch)
treeb27bedc317d68e969e9220cb93de8bc9fc5c62e8 /arch/arm/mach-imx/gpc.c
parent1103643c266ae45c7098e0f7f3ee0b68e3e7c7cc (diff)
arm/imx6q: add core drivers clock, gpc, mmdc and src
It adds a number of core drivers support for imx6q, including clock, General Power Controller (gpc), Multi Mode DDR Controller(mmdc) and System Reset Controller (src). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/gpc.c')
-rw-r--r--arch/arm/mach-imx/gpc.c113
1 files changed, 113 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
new file mode 100644
index 00000000000..e1537f9e45b
--- /dev/null
+++ b/arch/arm/mach-imx/gpc.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/hardware/gic.h>
+
+#define GPC_IMR1 0x008
+#define GPC_PGC_CPU_PDN 0x2a0
+
+#define IMR_NUM 4
+
+static void __iomem *gpc_base;
+static u32 gpc_wake_irqs[IMR_NUM];
+static u32 gpc_saved_imrs[IMR_NUM];
+
+void imx_gpc_pre_suspend(void)
+{
+ void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
+ int i;
+
+ /* Tell GPC to power off ARM core when suspend */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+
+ for (i = 0; i < IMR_NUM; i++) {
+ gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
+ writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
+ }
+}
+
+void imx_gpc_post_resume(void)
+{
+ void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
+ int i;
+
+ /* Keep ARM core powered on for other low-power modes */
+ writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
+
+ for (i = 0; i < IMR_NUM; i++)
+ writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
+}
+
+static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ unsigned int idx = d->irq / 32 - 1;
+ u32 mask;
+
+ /* Sanity check for SPI irq */
+ if (d->irq < 32)
+ return -EINVAL;
+
+ mask = 1 << d->irq % 32;
+ gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
+ gpc_wake_irqs[idx] & ~mask;
+
+ return 0;
+}
+
+static void imx_gpc_irq_unmask(struct irq_data *d)
+{
+ void __iomem *reg;
+ u32 val;
+
+ /* Sanity check for SPI irq */
+ if (d->irq < 32)
+ return;
+
+ reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+ val = readl_relaxed(reg);
+ val &= ~(1 << d->irq % 32);
+ writel_relaxed(val, reg);
+}
+
+static void imx_gpc_irq_mask(struct irq_data *d)
+{
+ void __iomem *reg;
+ u32 val;
+
+ /* Sanity check for SPI irq */
+ if (d->irq < 32)
+ return;
+
+ reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+ val = readl_relaxed(reg);
+ val |= 1 << (d->irq % 32);
+ writel_relaxed(val, reg);
+}
+
+void __init imx_gpc_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
+ gpc_base = of_iomap(np, 0);
+ WARN_ON(!gpc_base);
+
+ /* Register GPC as the secondary interrupt controller behind GIC */
+ gic_arch_extn.irq_mask = imx_gpc_irq_mask;
+ gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
+ gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
+}