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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-21 10:00:22 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-21 10:00:22 -0700
commitd07b3c25327c5ae3792d0ed0c135dee4727200a1 (patch)
tree2ffad8da1f9004bdeb32bf76faa08fa104797b89 /arch/arm/mach-iop13xx
parentdde33348e53ecab687a9768bf5262f0b8f79b7f2 (diff)
parent6cbdc8c5357276307a77deeada3f04626ff17da6 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits) [ARM] spelling fixes [ARM] at91_adc parenthesis balance [ARM] 4400/1: S3C24XX: Add high-speed MMC device definition [ARM] 4399/2: S3C2443: Fix SMDK2443 nand timings [ARM] 4398/1: S3C2443: Fix watchdog IRQ number [ARM] 4397/1: S3C2443: remove SDI0/1 IRQ ambiguity [ARM] 4396/1: S3C2443: Add missing HCLK clocks [ARM] 4395/1: S3C24XX: add include of <linux/sysdev.h> to relevant machines [ARM] 4388/1: no need for arm/mm mmap range checks for non-mmu [ARM] 4387/1: fix /proc/cpuinfo formatting for pre-ARM7 parts [ARM] ARMv6: add CPU_HAS_ASID configuration [ARM] integrator: fix pci_v3 compile error with DEBUG_LL [ARM] gic: Fix gic cascade irq handling [ARM] Silence OMAP kernel configuration warning [ARM] Update ARM syscalls [ARM] 4384/1: S3C2412/13 SPI registers offset correction [ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files [ARM] 4382/1: iop13xx: fix msi support [ARM] Remove Integrator/CP SMP platform support [ARM] 4378/1: KS8695: Serial driver fix ...
Diffstat (limited to 'arch/arm/mach-iop13xx')
-rw-r--r--arch/arm/mach-iop13xx/irq.c54
-rw-r--r--arch/arm/mach-iop13xx/msi.c18
-rw-r--r--arch/arm/mach-iop13xx/pci.c10
3 files changed, 23 insertions, 59 deletions
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index 5791addd436..69f07b25b3c 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -30,77 +30,65 @@
/* INTCTL0 CP6 R0 Page 4
*/
-static inline u32 read_intctl_0(void)
+static u32 read_intctl_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
return val;
}
-static inline void write_intctl_0(u32 val)
+static void write_intctl_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
}
/* INTCTL1 CP6 R1 Page 4
*/
-static inline u32 read_intctl_1(void)
+static u32 read_intctl_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
return val;
}
-static inline void write_intctl_1(u32 val)
+static void write_intctl_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
}
/* INTCTL2 CP6 R2 Page 4
*/
-static inline u32 read_intctl_2(void)
+static u32 read_intctl_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
return val;
}
-static inline void write_intctl_2(u32 val)
+static void write_intctl_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
}
/* INTCTL3 CP6 R3 Page 4
*/
-static inline u32 read_intctl_3(void)
+static u32 read_intctl_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
return val;
}
-static inline void write_intctl_3(u32 val)
+static void write_intctl_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
}
/* INTSTR0 CP6 R0 Page 5
*/
-static inline u32 read_intstr_0(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
- return val;
-}
-static inline void write_intstr_0(u32 val)
+static void write_intstr_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
}
/* INTSTR1 CP6 R1 Page 5
*/
-static inline u32 read_intstr_1(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
- return val;
-}
static void write_intstr_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
@@ -108,12 +96,6 @@ static void write_intstr_1(u32 val)
/* INTSTR2 CP6 R2 Page 5
*/
-static inline u32 read_intstr_2(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
- return val;
-}
static void write_intstr_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
@@ -121,12 +103,6 @@ static void write_intstr_2(u32 val)
/* INTSTR3 CP6 R3 Page 5
*/
-static inline u32 read_intstr_3(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
- return val;
-}
static void write_intstr_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
@@ -134,12 +110,6 @@ static void write_intstr_3(u32 val)
/* INTBASE CP6 R0 Page 2
*/
-static inline u32 read_intbase(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
- return val;
-}
static void write_intbase(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
@@ -147,12 +117,6 @@ static void write_intbase(u32 val)
/* INTSIZE CP6 R2 Page 2
*/
-static inline u32 read_intsize(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
- return val;
-}
static void write_intsize(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index 2d236930222..63ef1124ca5 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -30,52 +30,52 @@ static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
/* IMIPR0 CP6 R8 Page 1
*/
-static inline u32 read_imipr_0(void)
+static u32 read_imipr_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
return val;
}
-static inline void write_imipr_0(u32 val)
+static void write_imipr_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
}
/* IMIPR1 CP6 R9 Page 1
*/
-static inline u32 read_imipr_1(void)
+static u32 read_imipr_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
return val;
}
-static inline void write_imipr_1(u32 val)
+static void write_imipr_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
}
/* IMIPR2 CP6 R10 Page 1
*/
-static inline u32 read_imipr_2(void)
+static u32 read_imipr_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
return val;
}
-static inline void write_imipr_2(u32 val)
+static void write_imipr_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
}
/* IMIPR3 CP6 R11 Page 1
*/
-static inline u32 read_imipr_3(void)
+static u32 read_imipr_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
return val;
}
-static inline void write_imipr_3(u32 val)
+static void write_imipr_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
}
@@ -190,5 +190,5 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
write_msi_msg(irq, &msg);
set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
- return irq;
+ return 0;
}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 6baeb26c3aa..9d63d7f260c 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -145,7 +145,7 @@ void iop13xx_map_pci_memory(void)
}
}
-static inline int iop13xx_atu_function(int atu)
+static int iop13xx_atu_function(int atu)
{
int func = 0;
/* the function number depends on the value of the
@@ -260,7 +260,7 @@ static int iop13xx_atux_pci_status(int clear)
* data. Note that the data dependency on %0 encourages an abort
* to be detected before we return.
*/
-static inline u32 iop13xx_atux_read(unsigned long addr)
+static u32 iop13xx_atux_read(unsigned long addr)
{
u32 val;
@@ -388,7 +388,7 @@ static int iop13xx_atue_pci_status(int clear)
return err;
}
-static inline int __init
+static int
iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
WARN_ON(idsel != 0);
@@ -402,7 +402,7 @@ iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
}
}
-static inline u32 iop13xx_atue_read(unsigned long addr)
+static u32 iop13xx_atue_read(unsigned long addr)
{
u32 val;
@@ -990,7 +990,7 @@ void __init iop13xx_pci_init(void)
"imprecise external abort");
}
-/* intialize the pci memory space. handle any combination of
+/* initialize the pci memory space. handle any combination of
* atue and atux enabled/disabled
*/
int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)