diff options
| author | Len Brown <len.brown@intel.com> | 2009-04-05 02:14:15 -0400 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2009-04-05 02:14:15 -0400 |
| commit | 478c6a43fcbc6c11609f8cee7c7b57223907754f (patch) | |
| tree | a7f7952099da60d33032aed6de9c0c56c9f8779e /arch/arm/mach-ixp4xx/common-pci.c | |
| parent | 8a3f257c704e02aee9869decd069a806b45be3f1 (diff) | |
| parent | 6bb597507f9839b13498781e481f5458aea33620 (diff) | |
Merge branch 'linus' into release
Conflicts:
arch/x86/kernel/cpu/cpufreq/longhaul.c
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/arm/mach-ixp4xx/common-pci.c')
| -rw-r--r-- | arch/arm/mach-ixp4xx/common-pci.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index d816c51320c..70afcfe5b88 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -366,7 +366,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, } void __init ixp4xx_pci_preinit(void) -{ +{ unsigned long cpuid = read_cpuid_id(); /* @@ -386,17 +386,17 @@ void __init ixp4xx_pci_preinit(void) pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); - /* + /* * We use identity AHB->PCI address translation * in the 0x48000000 to 0x4bffffff address space */ *PCI_PCIMEMBASE = 0x48494A4B; - /* + /* * We also use identity PCI->AHB address translation * in 4 16MB BARs that begin at the physical memory start */ - *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + + *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + ((PHYS_OFFSET & 0xFF000000) >> 8) + ((PHYS_OFFSET & 0xFF000000) >> 16) + ((PHYS_OFFSET & 0xFF000000) >> 24) + @@ -408,18 +408,19 @@ void __init ixp4xx_pci_preinit(void) pr_debug("setup BARs in controller\n"); /* - * We configure the PCI inbound memory windows to be + * We configure the PCI inbound memory windows to be * 1:1 mapped to SDRAM */ - local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000); - local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000); - local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000); - local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000); + local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET); + local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M); + local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); + local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M); /* - * Enable CSR window at 0xff000000. + * Enable CSR window at 64 MiB to allow PCI masters + * to continue prefetching past 64 MiB boundary. */ - local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008); + local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M); /* * Enable the IO window to be way up high, at 0xfffffc00 @@ -500,7 +501,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) return 1; } -struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) { return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); } |