diff options
| author | Ingo Molnar <mingo@elte.hu> | 2009-04-29 14:46:59 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-04-29 14:47:05 +0200 |
| commit | e7fd5d4b3d240f42c30a9e3d20a4689c4d3a795a (patch) | |
| tree | 4ba588631dd8189a818a91c9e3976526071178b6 /arch/arm/mach-kirkwood/include/mach/kirkwood.h | |
| parent | 1130b0296184bc21806225fd06d533515a99d2db (diff) | |
| parent | 56a50adda49b2020156616c4eb15353e0f9ad7de (diff) | |
Merge branch 'linus' into perfcounters/core
Merge reason: This brach was on -rc1, refresh it to almost-rc4 to pick up
the latest upstream fixes.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mach-kirkwood/include/mach/kirkwood.h')
| -rw-r--r-- | arch/arm/mach-kirkwood/include/mach/kirkwood.h | 53 |
1 files changed, 15 insertions, 38 deletions
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index 38c98685359..b3e13958821 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -44,44 +44,6 @@ #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M /* - * MBUS bridge registers. - */ -#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) -#define CPU_RESET 0x00000002 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) -#define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) -#define SOFT_RESET 0x00000001 -#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) -#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) -#define BRIDGE_INT_TIMER0 0x0002 -#define BRIDGE_INT_TIMER1 0x0004 -#define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) -#define IRQ_CAUSE_LOW_OFF 0x0000 -#define IRQ_MASK_LOW_OFF 0x0004 -#define IRQ_CAUSE_HIGH_OFF 0x0010 -#define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) -#define L2_WRITETHROUGH 0x00000010 - -/* - * Supported devices and revisions. - */ -#define MV88F6281_DEV_ID 0x6281 -#define MV88F6281_REV_Z0 0 -#define MV88F6281_REV_A0 2 - -#define MV88F6192_DEV_ID 0x6192 -#define MV88F6192_REV_Z0 0 -#define MV88F6192_REV_A0 2 - -#define MV88F6180_DEV_ID 0x6180 -#define MV88F6180_REV_A0 2 - -/* * Register Map */ #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) @@ -99,6 +61,8 @@ #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) +#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) + #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) @@ -119,5 +83,18 @@ #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) +/* + * Supported devices and revisions. + */ +#define MV88F6281_DEV_ID 0x6281 +#define MV88F6281_REV_Z0 0 +#define MV88F6281_REV_A0 2 + +#define MV88F6192_DEV_ID 0x6192 +#define MV88F6192_REV_Z0 0 +#define MV88F6192_REV_A0 2 + +#define MV88F6180_DEV_ID 0x6180 +#define MV88F6180_REV_A0 2 #endif |