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authorSrinidhi Kasagar <srinidhi.kasagar@stericsson.com>2011-02-17 07:03:51 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-02-19 11:23:21 +0000
commit885028e4ba4caf49d565c96481e1a05220ecb517 (patch)
tree45be55a3aa9cbd14bf924e00f974c43a35c573bc /arch/arm/mach-l7200
parent0cc9d5257857608ba85885b75fcada13d359b5d1 (diff)
ARM: 6741/1: errata: pl310 cache sync operation may be faulty
The effect of cache sync operation is to drain the store buffer and wait for all internal buffers to be empty. In normal conditions, store buffer is able to merge the normal memory writes within its 32-byte data buffers. Due to this erratum present in r3p0, the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes. This can severely affect performance on the write traffic esp. on Normal memory NC one. The proposed workaround is to replace the normal offset of cache sync operation(0x730) by another offset targeting an unmapped PL310 register 0x740. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-l7200')
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