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authorEric Bénard <eric@eukrea.com>2010-07-21 14:46:11 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2010-07-26 15:05:21 +0200
commitaa8721431909c9afa611373c7edfb7f514a6ad83 (patch)
tree4202813835b9f9a151ffd961748cdff1db30752a /arch/arm/mach-mx5/devices.c
parent5055d1efc0cb4bd612c78af8fa61316ae49755a9 (diff)
i.MX51: handle IRQ for gpio 16..31
The i.MX51 generates 2 IRQ for each GPIO bank : one for gpio 0 to 15 and one for gpio 16 to 31. Actually only the lower IRQ is registered so register the second one. Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx5/devices.c')
-rw-r--r--arch/arm/mach-mx5/devices.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index aafa61c6cec..1920ff4963b 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -250,24 +250,28 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
.chip.label = "gpio-0",
.base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
.irq = MX51_MXC_INT_GPIO1_LOW,
+ .irq_high = MX51_MXC_INT_GPIO1_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START
},
{
.chip.label = "gpio-1",
.base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
.irq = MX51_MXC_INT_GPIO2_LOW,
+ .irq_high = MX51_MXC_INT_GPIO2_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
},
{
.chip.label = "gpio-2",
.base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
.irq = MX51_MXC_INT_GPIO3_LOW,
+ .irq_high = MX51_MXC_INT_GPIO3_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
},
{
.chip.label = "gpio-3",
.base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
.irq = MX51_MXC_INT_GPIO4_LOW,
+ .irq_high = MX51_MXC_INT_GPIO4_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
},
};