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| author | Ingo Molnar <mingo@elte.hu> | 2011-04-19 07:55:58 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2011-04-19 07:56:17 +0200 |
| commit | 68d2cf25d39324c54b5e42de7915c623a0917abe (patch) | |
| tree | ff1291450d7e6630bc77ec1363c3db8d74fa58b0 /arch/arm/mach-mxs/clock-mx23.c | |
| parent | 176fcc5c5f0131504a55e1e1d35389c49a9177c2 (diff) | |
| parent | 5d2cd90922c778908bd0cd669e572a5b5eafd737 (diff) | |
Merge branch 'perf/urgent' into perf/core
Merge reason: we'll be queueing up dependent changes.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mach-mxs/clock-mx23.c')
| -rw-r--r-- | arch/arm/mach-mxs/clock-mx23.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index d133c7f3094..c3577ea789a 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -521,6 +521,15 @@ static int clk_misc_init(void) __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); + /* + * 480 MHz seems too high to be ssp clock source directly, + * so set frac to get a 288 MHz ref_io. + */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + reg &= ~BM_CLKCTRL_FRAC_IOFRAC; + reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + return 0; } @@ -528,6 +537,12 @@ int __init mx23_clocks_init(void) { clk_misc_init(); + /* + * source ssp clock from ref_io than ref_xtal, + * as ref_xtal only provides 24 MHz as maximum. + */ + clk_set_parent(&ssp_clk, &ref_io_clk); + clk_enable(&cpu_clk); clk_enable(&hbus_clk); clk_enable(&xbus_clk); |