ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts

Clean all #ifdef's added to common clock code.  This code is no longer
needed due to migration to the common clock framework.

Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul@pwsan.com: clean up new ifdefs added in clockdomain.c]
Signed-off-by: Paul Walmsley <paul@pwsan.com>

1 files changed, 0 insertions, 238 deletions

diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 03ceb2efd53..0ec9f6fdf04 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -41,11 +41,7 @@
 
 #include <linux/kernel.h>
 #include <linux/errno.h>
-#ifdef CONFIG_COMMON_CLK
 #include <linux/clk-provider.h>
-#else
-#include <linux/clk.h>
-#endif
 #include <linux/io.h>
 #include <linux/bug.h>
 
@@ -62,11 +58,7 @@
  * the element associated with the supplied parent clock address.
  * Returns a pointer to the struct clksel on success or NULL on error.
  */
-#ifdef CONFIG_COMMON_CLK
 static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk,
-#else
-static const struct clksel *_get_clksel_by_parent(struct clk *clk,
-#endif
 						  struct clk *src_clk)
 {
 	const struct clksel *clks;
@@ -81,11 +73,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
 	if (!clks->parent) {
 		/* This indicates a data problem */
 		WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
-#ifdef CONFIG_COMMON_CLK
 		     __clk_get_name(clk->hw.clk), __clk_get_name(src_clk));
-#else
-		     __clk_get_name(clk), __clk_get_name(src_clk));
-#endif
 		return NULL;
 	}
 
@@ -93,66 +81,6 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
 }
 
 /**
- * _get_div_and_fieldval() - find the new clksel divisor and field value to use
- * @src_clk: planned new parent struct clk *
- * @clk: struct clk * that is being reparented
- * @field_val: pointer to a u32 to contain the register data for the divisor
- *
- * Given an intended new parent struct clk * @src_clk, and the struct
- * clk * @clk to the clock that is being reparented, find the
- * appropriate rate divisor for the new clock (returned as the return
- * value), and the corresponding register bitfield data to program to
- * reach that divisor (returned in the u32 pointed to by @field_val).
- * Returns 0 on error, or returns the newly-selected divisor upon
- * success (in this latter case, the corresponding register bitfield
- * value is passed back in the variable pointed to by @field_val)
- */
-#ifndef CONFIG_COMMON_CLK
-static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
-				u32 *field_val)
-{
-	const struct clksel *clks;
-	const struct clksel_rate *clkr, *max_clkr = NULL;
-	u8 max_div = 0;
-
-	clks = _get_clksel_by_parent(clk, src_clk);
-	if (!clks)
-		return 0;
-
-	/*
-	 * Find the highest divisor (e.g., the one resulting in the
-	 * lowest rate) to use as the default.  This should avoid
-	 * clock rates that are too high for the device.  XXX A better
-	 * solution here would be to try to determine if there is a
-	 * divisor matching the original clock rate before the parent
-	 * switch, and if it cannot be found, to fall back to the
-	 * highest divisor.
-	 */
-	for (clkr = clks->rates; clkr->div; clkr++) {
-		if (!(clkr->flags & cpu_mask))
-			continue;
-
-		if (clkr->div > max_div) {
-			max_div = clkr->div;
-			max_clkr = clkr;
-		}
-	}
-
-	if (max_div == 0) {
-		/* This indicates an error in the clksel data */
-		WARN(1, "clock: %s: could not find divisor for parent %s\n",
-		     __clk_get_name(clk),
-		     __clk_get_name(__clk_get_parent(src_clk)));
-		return 0;
-	}
-
-	*field_val = max_clkr->val;
-
-	return max_div;
-}
-#endif
-
-/**
  * _write_clksel_reg() - program a clock's clksel register in hardware
  * @clk: struct clk * to program
  * @v: clksel bitfield value to program (with LSB at bit 0)
@@ -165,11 +93,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
  * take into account any time the hardware might take to switch the
  * clock source.
  */
-#ifdef CONFIG_COMMON_CLK
 static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
-#else
-static void _write_clksel_reg(struct clk *clk, u32 field_val)
-#endif
 {
 	u32 v;
 
@@ -192,21 +116,13 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val)
  * before calling.  Returns 0 on error or returns the actual integer divisor
  * upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val)
-#else
-static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
-#endif
 {
 	const struct clksel *clks;
 	const struct clksel_rate *clkr;
 	struct clk *parent;
 
-#ifdef CONFIG_COMMON_CLK
 	parent = __clk_get_parent(clk->hw.clk);
-#else
-	parent = __clk_get_parent(clk);
-#endif
 
 	clks = _get_clksel_by_parent(clk, parent);
 	if (!clks)
@@ -223,12 +139,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 	if (!clkr->div) {
 		/* This indicates a data error */
 		WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
-#ifdef CONFIG_COMMON_CLK
 		     __clk_get_name(clk->hw.clk), field_val,
 		     __clk_get_name(parent));
-#else
-		     __clk_get_name(clk), field_val, __clk_get_name(parent));
-#endif
 		return 0;
 	}
 
@@ -245,11 +157,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
  * register field value _before_ left-shifting (i.e., LSB is at bit
  * 0); or returns 0xFFFFFFFF (~0) upon error.
  */
-#ifdef CONFIG_COMMON_CLK
 static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div)
-#else
-static u32 _divisor_to_clksel(struct clk *clk, u32 div)
-#endif
 {
 	const struct clksel *clks;
 	const struct clksel_rate *clkr;
@@ -258,11 +166,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 	/* should never happen */
 	WARN_ON(div == 0);
 
-#ifdef CONFIG_COMMON_CLK
 	parent = __clk_get_parent(clk->hw.clk);
-#else
-	parent = __clk_get_parent(clk);
-#endif
 	clks = _get_clksel_by_parent(clk, parent);
 	if (!clks)
 		return ~0;
@@ -277,12 +181,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 
 	if (!clkr->div) {
 		pr_err("clock: %s: could not find divisor %d for parent %s\n",
-#ifdef CONFIG_COMMON_CLK
 		       __clk_get_name(clk->hw.clk), div,
 		       __clk_get_name(parent));
-#else
-		       __clk_get_name(clk), div, __clk_get_name(parent));
-#endif
 		return ~0;
 	}
 
@@ -297,11 +197,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
  * into the hardware, convert it into the actual divisor value, and
  * return it; or return 0 on error.
  */
-#ifdef CONFIG_COMMON_CLK
 static u32 _read_divisor(struct clk_hw_omap *clk)
-#else
-static u32 _read_divisor(struct clk *clk)
-#endif
 {
 	u32 v;
 
@@ -329,12 +225,8 @@ static u32 _read_divisor(struct clk *clk)
  *
  * Returns the rounded clock rate or returns 0xffffffff on error.
  */
-#ifdef CONFIG_COMMON_CLK
 u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
 						 unsigned long target_rate,
-#else
-u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
-#endif
 				u32 *new_div)
 {
 	unsigned long test_rate;
@@ -345,13 +237,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 	unsigned long parent_rate;
 	const char *clk_name;
 
-#ifdef CONFIG_COMMON_CLK
 	parent = __clk_get_parent(clk->hw.clk);
 	clk_name = __clk_get_name(clk->hw.clk);
-#else
-	parent = __clk_get_parent(clk);
-	clk_name = __clk_get_name(clk);
-#endif
 	parent_rate = __clk_get_rate(parent);
 
 	if (!clk->clksel || !clk->clksel_mask)
@@ -402,7 +289,6 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
  * (i.e., those used in struct clk field function pointers, etc.)
  */
 
-#ifdef CONFIG_COMMON_CLK
 /**
  * omap2_clksel_find_parent_index() - return the array index of the current
  * hardware parent of @hw
@@ -457,62 +343,6 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
 	return ret;
 }
 
-#else
-
-/**
- * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
- * @clk: OMAP clock struct ptr to use
- *
- * Given a pointer @clk to a source-selectable struct clk, read the
- * hardware register and determine what its parent is currently set
- * to.  Update @clk's .parent field with the appropriate clk ptr.  No
- * return value.
- */
-void omap2_init_clksel_parent(struct clk *clk)
-{
-	const struct clksel *clks;
-	const struct clksel_rate *clkr;
-	u32 r, found = 0;
-	struct clk *parent;
-	const char *clk_name;
-
-	if (!clk->clksel || !clk->clksel_mask)
-		return;
-
-	parent = __clk_get_parent(clk);
-	clk_name = __clk_get_name(clk);
-
-	r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
-	r >>= __ffs(clk->clksel_mask);
-
-	for (clks = clk->clksel; clks->parent && !found; clks++) {
-		for (clkr = clks->rates; clkr->div && !found; clkr++) {
-			if (!(clkr->flags & cpu_mask))
-				continue;
-
-			if (clkr->val == r) {
-				if (parent != clks->parent) {
-					pr_debug("clock: %s: inited parent to %s (was %s)\n",
-						 clk_name,
-						 __clk_get_name(clks->parent),
-						 ((parent) ?
-						  __clk_get_name(parent) :
-						 "NULL"));
-					clk_reparent(clk, clks->parent);
-				}
-				found = 1;
-			}
-		}
-	}
-
-	/* This indicates a data error */
-	WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
-	     clk_name, r);
-
-	return;
-}
-
-#endif
 
 /**
  * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
@@ -523,7 +353,6 @@ void omap2_init_clksel_parent(struct clk *clk)
  * function.  Returns the clock's current rate, based on its parent's rate
  * and its current divisor setting in the hardware.
  */
-#ifdef CONFIG_COMMON_CLK
 unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
 {
 	unsigned long rate;
@@ -544,26 +373,6 @@ unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
 
 	return rate;
 }
-#else
-unsigned long omap2_clksel_recalc(struct clk *clk)
-{
-	unsigned long rate;
-	u32 div = 0;
-	struct clk *parent;
-
-	div = _read_divisor(clk);
-	if (div == 0)
-		return __clk_get_rate(clk);
-
-	parent = __clk_get_parent(clk);
-	rate = __clk_get_rate(parent) / div;
-
-	pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
-		 __clk_get_name(clk), rate, div);
-
-	return rate;
-}
-#endif
 
 /**
  * omap2_clksel_round_rate() - find rounded rate for the given clock and rate
@@ -576,15 +385,10 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
  *
  * Returns the rounded clock rate or returns 0xffffffff on error.
  */
-#ifdef CONFIG_COMMON_CLK
 long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
 			unsigned long *parent_rate)
 {
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
-{
-#endif
 	u32 new_div;
 
 	return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
@@ -605,15 +409,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
  * is changed, they will all be affected without any notification.
  * Returns -EINVAL upon error, or 0 upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
 				unsigned long parent_rate)
 {
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
-{
-#endif
 	u32 field_val, validrate, new_div = 0;
 
 	if (!clk->clksel || !clk->clksel_mask)
@@ -629,15 +428,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 
 	_write_clksel_reg(clk, field_val);
 
-#ifdef CONFIG_COMMON_CLK
 	pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk),
 		 __clk_get_rate(hw->clk));
-#else
-	pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
-		 __clk_get_rate(clk));
-
-	clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
-#endif
 
 	return 0;
 }
@@ -662,7 +454,6 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
  * affected without any notification.  Returns -EINVAL upon error, or
  * 0 upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
 {
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
@@ -673,32 +464,3 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
 	_write_clksel_reg(clk, field_val);
 	return 0;
 }
-#else
-int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
-{
-	u32 field_val = 0;
-	u32 parent_div;
-
-	if (!clk->clksel || !clk->clksel_mask)
-		return -EINVAL;
-
-	parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
-	if (!parent_div)
-		return -EINVAL;
-	_write_clksel_reg(clk, field_val);
-
-	clk_reparent(clk, new_parent);
-
-	/* CLKSEL clocks follow their parents' rates, divided by a divisor */
-	clk->rate = __clk_get_rate(new_parent);
-
-	if (parent_div > 0)
-		__clk_get_rate(clk) /= parent_div;
-	pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
-		 __clk_get_name(clk),
-		 __clk_get_name(__clk_get_parent(clk)),
-		 __clk_get_rate(clk));
-
-	return 0;
-}
-#endif