Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6

* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (26 commits)
  OMAP2 clock: dynamically allocate CPUFreq frequency table
  OMAP clock/CPUFreq: add clk_exit_cpufreq_table()
  OMAP2xxx OPP: clean up comments in OPP data
  OMAP2xxx clock: clk2xxx.c doesn't compile if CPUFREQ is enabled
  OMAP1 clock: remove __initdata from struct clk_functions to prevent crash
  OMAP1 clock: Add missing clocks for OMAP 7xx
  OMAP clock: remove incorrect EXPORT_SYMBOL()s
  OMAP3 clock: Add capability to change rate of dpll4_m5_ck
  OMAP3 clock: McBSP 2, 3, 4 functional clock parent is PER_96M_FCLK, not CORE_96M_FCLK
  OMAP3: clock: add clockdomains for UART1 & 2
  OMAP2420 IO mapping: move IVA mapping virtual address out of vmalloc space
  OMAP2xxx IO mapping: mark DSP mappings as being 2420-only
  ARM: OMAP3: PM: Fix the Invalid CM_CLKSTCTRL reg access.
  OMAP2: remove duplicated #include
  omap3: EVM: Choose OMAP_PACKAGE_CBB
  omap3: Fix booting if package is uninitialized
  omap3: add missing parentheses
  omap3: add missing parentheses
  omap2/3: ZOOM: Correcting key mapping for few keys
  omap2/3: make serial_in_override() address the right uart port
  ...

1 files changed, 5 insertions, 1 deletions

diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index 8bdcc9cc7f9..c6031d74d6f 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -776,6 +776,8 @@ static struct clk dpll4_m5_ck = {
 	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,
 	.clksel		= div16_dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
+	.set_rate	= &omap2_clksel_set_rate,
+	.round_rate	= &omap2_clksel_round_rate,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -1500,6 +1502,7 @@ static struct clk uart2_fck = {
 	.parent		= &core_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_UART2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 
@@ -1509,6 +1512,7 @@ static struct clk uart1_fck = {
 	.parent		= &core_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_UART1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 
@@ -2745,7 +2749,7 @@ static struct clk mcbsp4_ick = {
 };
 
 static const struct clksel mcbsp_234_clksel[] = {
-	{ .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+	{ .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
 	{ .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
 	{ .parent = NULL }
 };