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authorRajendra Nayak <rnayak@ti.com>2012-04-27 15:53:48 +0530
committerPaul Walmsley <paul@pwsan.com>2012-11-12 19:10:18 -0700
commitb4777a21381fd1f87be8c606a616b7f97f485d2b (patch)
treeaf45be72d14dde6fc899ac2ad5f9984f1bfa5cd5 /arch/arm/mach-omap2/clock3xxx.c
parent32cc002116b866151ca24c6e9110ba8a93754753 (diff)
ARM: OMAP3: clock: Convert to common clk
Convert all OMAP3 specific platform files to use COMMON clk and keep all the changes under the CONFIG_COMMON_CLK macro check so it does not break any existing code. At a later point switch to COMMON clk and get rid of all old/legacy code. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx.c')
-rw-r--r--arch/arm/mach-omap2/clock3xxx.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 3e8aca2b1b6..a6f75cd8532 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -38,8 +38,12 @@
/* needed by omap3_core_dpll_m2_set_rate() */
struct clk *sdrc_ick_p, *arm_fck_p;
-
+#ifdef CONFIG_COMMON_CLK
+int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+#else
int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
+#endif
{
/*
* According to the 12-5 CDP code from TI, "Limitation 2.5"
@@ -51,7 +55,11 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
return -EINVAL;
}
+#ifdef CONFIG_COMMON_CLK
+ return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
+#else
return omap3_noncore_dpll_set_rate(clk, rate);
+#endif
}
void __init omap3_clk_lock_dpll5(void)