Merge tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC Non-critical bug fixes from Olof Johansson:
 "Simple bug fixes that were not considered important enough for
  inclusion into 3.7, especially those that arrived late during the
  merge window.

  There's also a MAINTAINERS update for the Renesas platforms in here,
  marking Simon Horman as a maintainer and changing the git url to his
  tree."

* tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  Update ARM/SHMOBILE section of MAINTAINERS
  ARM: Fix Kconfig symbols typo for LEDS
  ARM: pxa: add dummy SA1100 rtc clock in pxa25x
  ARM: pxa: fix pxa25x gpio wakeup setting
  ARM: OMAP4: PM: fix errata handling when CONFIG_PM=n
  ARM: cns3xxx: drop unnecessary symbol selection
  ARM: vexpress: fix ll debug code when building multiplatform
  ARM: OMAP4: retrigger localtimers after re-enabling gic
  ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
  ARM: OMAP4: PM: add errata support
  ARM: davinci: fix return value check by using IS_ERR in tnetv107x_devices_init()
  ARM: davinci: uncompress.h: bail out if uart not initialized
  ARM: davinci: serial.h: fix uart number in the comment
  ARM: davinci: dm644x evm: move pointer dereference below NULL check
  ARM: vexpress: Make the debug UART detection more specific

1 files changed, 38 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 502e3135aad..0ea09faf327 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -18,6 +18,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include "omap44xx.h"
+
 	__CPUINIT
 
 /* Physical address needed since MMU not enabled yet on secondary core */
@@ -64,3 +66,39 @@ hold:	ldr	r12,=0x103
 	b	secondary_startup
 ENDPROC(omap_secondary_startup)
 
+ENTRY(omap_secondary_startup_4460)
+hold_2:	ldr	r12,=0x103
+	dsb
+	smc	#0			@ read from AuxCoreBoot0
+	mov	r0, r0, lsr #9
+	mrc	p15, 0, r4, c0, c0, 5
+	and	r4, r4, #0x0f
+	cmp	r0, r4
+	bne	hold_2
+
+	/*
+	 * GIC distributor control register has changed between
+	 * CortexA9 r1pX and r2pX. The Control Register secure
+	 * banked version is now composed of 2 bits:
+	 * bit 0 == Secure Enable
+	 * bit 1 == Non-Secure Enable
+	 * The Non-Secure banked register has not changed
+	 * Because the ROM Code is based on the r1pX GIC, the CPU1
+	 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
+	 * The workaround must be:
+	 * 1) Before doing the CPU1 wakeup, CPU0 must disable
+	 * the GIC distributor
+	 * 2) CPU1 must re-enable the GIC distributor on
+	 * it's wakeup path.
+	 */
+	ldr	r1, =OMAP44XX_GIC_DIST_BASE
+	ldr	r0, [r1]
+	orr	r0, #1
+	str	r0, [r1]
+
+	/*
+	 * we've been released from the wait loop,secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	b	secondary_startup
+ENDPROC(omap_secondary_startup_4460)