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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2009-04-28 20:51:52 +0530
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2009-06-09 13:03:50 +0530
commit367cd31ee0cbc948fe3b83960b1dbf931e2eaa90 (patch)
tree7d9c666fa6da3efb4e206c9f6b5fc4200320e498 /arch/arm/mach-omap2/omap-headsmp.S
parentc7f7ff179cb9f2f1e0244ef2c80afbb93c74ce2a (diff)
ARM: OMAP4: SMP: Add OMAP4430 SMP board files
This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap-headsmp.S')
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S46
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
new file mode 100644
index 00000000000..4afadba0947
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -0,0 +1,46 @@
+/*
+ * Secondary CPU startup routine source file.
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ * Author:
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Interface functions needed for the SMP. This file is based on arm
+ * realview smp platform.
+ * Copyright (c) 2003 ARM Limited.
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+/* Physical address needed since MMU not enabled yet on secondary core */
+#define OMAP4_AUX_CORE_BOOT1_PA 0x48281804
+
+ __INIT
+
+/*
+ * OMAP4 specific entry point for secondary CPU to jump from ROM
+ * code. This routine also provides a holding flag into which
+ * secondary core is held until we're ready for it to initialise.
+ * The primary core will update the this flag using a hardware
+ * register AuxCoreBoot1.
+ */
+ENTRY(omap_secondary_startup)
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #0x0f
+hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1
+ ldr r2, [r1]
+ cmp r2, r0
+ bne hold
+
+ /*
+ * we've been released from the cpu_release,secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+