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authorAbhijit Pagare <abhijitpagare@ti.com>2010-01-26 20:12:51 -0700
committerPaul Walmsley <paul@pwsan.com>2010-01-26 20:12:51 -0700
commit3790300903e6a98ce5f5391f4d435959266f79e7 (patch)
treecd78bf9d180466df0cd5b2f0c5b5c46d6471a54e /arch/arm/mach-omap2/pm34xx.c
parentc6a6e6e203ee9a34fa53f773272f21d48b4e3454 (diff)
ARM: OMAP4: PM: OMAP4 Power Domain Porting Related Clean-up.
Module offsets were same for OMAP2 and OMAP3 while they differ for OMAP4. Hence we need different macros for identifying platform specific offsets. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/pm34xx.c')
-rw-r--r--arch/arm/mach-omap2/pm34xx.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 910a7acf542..f841a6e3361 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -685,7 +685,7 @@ static void __init omap3_iva_idle(void)
prm_write_mod_reg(OMAP3430_RST1_IVA2 |
OMAP3430_RST2_IVA2 |
OMAP3430_RST3_IVA2,
- OMAP3430_IVA2_MOD, RM_RSTCTRL);
+ OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
/* Enable IVA2 clock */
cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
@@ -696,7 +696,7 @@ static void __init omap3_iva_idle(void)
OMAP343X_CONTROL_IVA2_BOOTMOD);
/* Un-reset IVA2 */
- prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
+ prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
/* Disable IVA2 clock */
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
@@ -705,7 +705,7 @@ static void __init omap3_iva_idle(void)
prm_write_mod_reg(OMAP3430_RST1_IVA2 |
OMAP3430_RST2_IVA2 |
OMAP3430_RST3_IVA2,
- OMAP3430_IVA2_MOD, RM_RSTCTRL);
+ OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
}
static void __init omap3_d2d_idle(void)
@@ -728,8 +728,8 @@ static void __init omap3_d2d_idle(void)
/* reset modem */
prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
- CORE_MOD, RM_RSTCTRL);
- prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
+ CORE_MOD, OMAP2_RM_RSTCTRL);
+ prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
}
static void __init prcm_setup_regs(void)
@@ -916,13 +916,13 @@ static void __init prcm_setup_regs(void)
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
/* Clear any pending 'reset' flags */
- prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
+ prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
/* Clear any pending PRCM interrupts */
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);