diff options
| author | Paul Walmsley <paul@pwsan.com> | 2010-05-18 18:47:24 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2010-05-20 12:31:05 -0600 |
| commit | 2bc4ef71c5a3b6986b452d6c530777974d11ef4a (patch) | |
| tree | fbb479aae791394b75fd598d279bb52cf015042d /arch/arm/mach-omap2/prm-regbits-34xx.h | |
| parent | f38ca10a79a0cd9902b8a470901951354802faa1 (diff) | |
OMAP3 PRCM: convert OMAP3 PRCM macros to the _SHIFT/_MASK suffixes
Fix all of the remaining OMAP3 PRCM register shift/bitmask macros that
did not use the _SHIFT/_MASK suffixes to use them. This makes the use
of these macros consistent. It is intended to reduce error, as code
can be inspected visually by reviewers to ensure that bitshifts and
bitmasks are used in the appropriate places.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/prm-regbits-34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-34xx.h | 360 |
1 files changed, 180 insertions, 180 deletions
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 8f21bae6dc1..7fd6023edf9 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -35,10 +35,10 @@ #define OMAP3430_ERRORGAIN_MASK (0xff << 16) #define OMAP3430_INITVOLTAGE_SHIFT 8 #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) -#define OMAP3430_TIMEOUTEN (1 << 3) -#define OMAP3430_INITVDD (1 << 2) -#define OMAP3430_FORCEUPDATE (1 << 1) -#define OMAP3430_VPENABLE (1 << 0) +#define OMAP3430_TIMEOUTEN_MASK (1 << 3) +#define OMAP3430_INITVDD_MASK (1 << 2) +#define OMAP3430_FORCEUPDATE_MASK (1 << 1) +#define OMAP3430_VPENABLE_MASK (1 << 0) /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 @@ -65,53 +65,53 @@ #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ -#define OMAP3430_VPINIDLE (1 << 0) +#define OMAP3430_VPINIDLE_MASK (1 << 0) /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ #define OMAP3430_EN_PER_SHIFT 7 #define OMAP3430_EN_PER_MASK (1 << 7) /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ -#define OMAP3430_MEMORYCHANGE (1 << 3) +#define OMAP3430_MEMORYCHANGE_MASK (1 << 3) /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ -#define OMAP3430_LOGICSTATEST (1 << 2) +#define OMAP3430_LOGICSTATEST_MASK (1 << 2) /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ -#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) +#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) /* * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits */ -#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 -#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) +#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 +#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ -#define OMAP3430_WKUP_ST (1 << 0) +#define OMAP3430_WKUP_ST_MASK (1 << 0) /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ -#define OMAP3430_WKUP_EN (1 << 0) +#define OMAP3430_WKUP_EN_MASK (1 << 0) /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ -#define OMAP3430_GRPSEL_MMC2 (1 << 25) -#define OMAP3430_GRPSEL_MMC1 (1 << 24) -#define OMAP3430_GRPSEL_MCSPI4 (1 << 21) -#define OMAP3430_GRPSEL_MCSPI3 (1 << 20) -#define OMAP3430_GRPSEL_MCSPI2 (1 << 19) -#define OMAP3430_GRPSEL_MCSPI1 (1 << 18) -#define OMAP3430_GRPSEL_I2C3 (1 << 17) -#define OMAP3430_GRPSEL_I2C2 (1 << 16) -#define OMAP3430_GRPSEL_I2C1 (1 << 15) -#define OMAP3430_GRPSEL_UART2 (1 << 14) -#define OMAP3430_GRPSEL_UART1 (1 << 13) -#define OMAP3430_GRPSEL_GPT11 (1 << 12) -#define OMAP3430_GRPSEL_GPT10 (1 << 11) -#define OMAP3430_GRPSEL_MCBSP5 (1 << 10) -#define OMAP3430_GRPSEL_MCBSP1 (1 << 9) -#define OMAP3430_GRPSEL_HSOTGUSB (1 << 4) -#define OMAP3430_GRPSEL_D2D (1 << 3) +#define OMAP3430_GRPSEL_MMC2_MASK (1 << 25) +#define OMAP3430_GRPSEL_MMC1_MASK (1 << 24) +#define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21) +#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) +#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) +#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) +#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) +#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) +#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) +#define OMAP3430_GRPSEL_UART2_MASK (1 << 14) +#define OMAP3430_GRPSEL_UART1_MASK (1 << 13) +#define OMAP3430_GRPSEL_GPT11_MASK (1 << 12) +#define OMAP3430_GRPSEL_GPT10_MASK (1 << 11) +#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10) +#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9) +#define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4) +#define OMAP3430_GRPSEL_D2D_MASK (1 << 3) /* * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, @@ -119,49 +119,49 @@ */ #define OMAP3430_MEMONSTATE_SHIFT 16 #define OMAP3430_MEMONSTATE_MASK (0x3 << 16) -#define OMAP3430_MEMRETSTATE (1 << 8) +#define OMAP3430_MEMRETSTATE_MASK (1 << 8) /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ -#define OMAP3430_GRPSEL_GPIO6 (1 << 17) -#define OMAP3430_GRPSEL_GPIO5 (1 << 16) -#define OMAP3430_GRPSEL_GPIO4 (1 << 15) -#define OMAP3430_GRPSEL_GPIO3 (1 << 14) -#define OMAP3430_GRPSEL_GPIO2 (1 << 13) -#define OMAP3430_GRPSEL_UART3 (1 << 11) -#define OMAP3430_GRPSEL_GPT9 (1 << 10) -#define OMAP3430_GRPSEL_GPT8 (1 << 9) -#define OMAP3430_GRPSEL_GPT7 (1 << 8) -#define OMAP3430_GRPSEL_GPT6 (1 << 7) -#define OMAP3430_GRPSEL_GPT5 (1 << 6) -#define OMAP3430_GRPSEL_GPT4 (1 << 5) -#define OMAP3430_GRPSEL_GPT3 (1 << 4) -#define OMAP3430_GRPSEL_GPT2 (1 << 3) -#define OMAP3430_GRPSEL_MCBSP4 (1 << 2) -#define OMAP3430_GRPSEL_MCBSP3 (1 << 1) -#define OMAP3430_GRPSEL_MCBSP2 (1 << 0) +#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) +#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) +#define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15) +#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) +#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) +#define OMAP3430_GRPSEL_UART3_MASK (1 << 11) +#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10) +#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9) +#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8) +#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7) +#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6) +#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5) +#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4) +#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3) +#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) +#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) +#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ -#define OMAP3430_GRPSEL_IO (1 << 8) -#define OMAP3430_GRPSEL_SR2 (1 << 7) -#define OMAP3430_GRPSEL_SR1 (1 << 6) -#define OMAP3430_GRPSEL_GPIO1 (1 << 3) -#define OMAP3430_GRPSEL_GPT12 (1 << 1) -#define OMAP3430_GRPSEL_GPT1 (1 << 0) +#define OMAP3430_GRPSEL_IO_MASK (1 << 8) +#define OMAP3430_GRPSEL_SR2_MASK (1 << 7) +#define OMAP3430_GRPSEL_SR1_MASK (1 << 6) +#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) +#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) +#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) /* Bits specific to each register */ /* RM_RSTCTRL_IVA2 */ -#define OMAP3430_RST3_IVA2 (1 << 2) -#define OMAP3430_RST2_IVA2 (1 << 1) -#define OMAP3430_RST1_IVA2 (1 << 0) +#define OMAP3430_RST3_IVA2_MASK (1 << 2) +#define OMAP3430_RST2_IVA2_MASK (1 << 1) +#define OMAP3430_RST1_IVA2_MASK (1 << 0) /* RM_RSTST_IVA2 specific bits */ -#define OMAP3430_EMULATION_VSEQ_RST (1 << 13) -#define OMAP3430_EMULATION_VHWA_RST (1 << 12) -#define OMAP3430_EMULATION_IVA2_RST (1 << 11) -#define OMAP3430_IVA2_SW_RST3 (1 << 10) -#define OMAP3430_IVA2_SW_RST2 (1 << 9) -#define OMAP3430_IVA2_SW_RST1 (1 << 8) +#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13) +#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12) +#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11) +#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10) +#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9) +#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8) /* PM_WKDEP_IVA2 specific bits */ @@ -174,10 +174,10 @@ #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) -#define OMAP3430_L2FLATMEMRETSTATE (1 << 11) -#define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10) -#define OMAP3430_L1FLATMEMRETSTATE (1 << 9) -#define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8) +#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) +#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) +#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) +#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) /* PM_PWSTST_IVA2 specific bits */ #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 @@ -200,12 +200,12 @@ #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) /* PRM_IRQSTATUS_IVA2 specific bits */ -#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2) -#define OMAP3430_FORCEWKUP_ST (1 << 1) +#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2) +#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1) /* PRM_IRQENABLE_IVA2 specific bits */ -#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2) -#define OMAP3430_FORCEWKUP_EN (1 << 1) +#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2) +#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1) /* PRM_REVISION specific bits */ @@ -213,70 +213,70 @@ /* PRM_IRQSTATUS_MPU specific bits */ #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 -#define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25) -#define OMAP3430_VC_TIMEOUTERR_ST (1 << 24) -#define OMAP3430_VC_RAERR_ST (1 << 23) -#define OMAP3430_VC_SAERR_ST (1 << 22) -#define OMAP3430_VP2_TRANXDONE_ST (1 << 21) -#define OMAP3430_VP2_EQVALUE_ST (1 << 20) -#define OMAP3430_VP2_NOSMPSACK_ST (1 << 19) -#define OMAP3430_VP2_MAXVDD_ST (1 << 18) -#define OMAP3430_VP2_MINVDD_ST (1 << 17) -#define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16) -#define OMAP3430_VP1_TRANXDONE_ST (1 << 15) -#define OMAP3430_VP1_EQVALUE_ST (1 << 14) -#define OMAP3430_VP1_NOSMPSACK_ST (1 << 13) -#define OMAP3430_VP1_MAXVDD_ST (1 << 12) -#define OMAP3430_VP1_MINVDD_ST (1 << 11) -#define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10) -#define OMAP3430_IO_ST (1 << 9) -#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8) +#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25) +#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24) +#define OMAP3430_VC_RAERR_ST_MASK (1 << 23) +#define OMAP3430_VC_SAERR_ST_MASK (1 << 22) +#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) +#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20) +#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19) +#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18) +#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17) +#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16) +#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) +#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14) +#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13) +#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12) +#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11) +#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10) +#define OMAP3430_IO_ST_MASK (1 << 9) +#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8) #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 -#define OMAP3430_MPU_DPLL_ST (1 << 7) +#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7) #define OMAP3430_MPU_DPLL_ST_SHIFT 7 -#define OMAP3430_PERIPH_DPLL_ST (1 << 6) +#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6) #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 -#define OMAP3430_CORE_DPLL_ST (1 << 5) +#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5) #define OMAP3430_CORE_DPLL_ST_SHIFT 5 -#define OMAP3430_TRANSITION_ST (1 << 4) -#define OMAP3430_EVGENOFF_ST (1 << 3) -#define OMAP3430_EVGENON_ST (1 << 2) -#define OMAP3430_FS_USB_WKUP_ST (1 << 1) +#define OMAP3430_TRANSITION_ST_MASK (1 << 4) +#define OMAP3430_EVGENOFF_ST_MASK (1 << 3) +#define OMAP3430_EVGENON_ST_MASK (1 << 2) +#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1) /* PRM_IRQENABLE_MPU specific bits */ #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 -#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25) -#define OMAP3430_VC_TIMEOUTERR_EN (1 << 24) -#define OMAP3430_VC_RAERR_EN (1 << 23) -#define OMAP3430_VC_SAERR_EN (1 << 22) -#define OMAP3430_VP2_TRANXDONE_EN (1 << 21) -#define OMAP3430_VP2_EQVALUE_EN (1 << 20) -#define OMAP3430_VP2_NOSMPSACK_EN (1 << 19) -#define OMAP3430_VP2_MAXVDD_EN (1 << 18) -#define OMAP3430_VP2_MINVDD_EN (1 << 17) -#define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16) -#define OMAP3430_VP1_TRANXDONE_EN (1 << 15) -#define OMAP3430_VP1_EQVALUE_EN (1 << 14) -#define OMAP3430_VP1_NOSMPSACK_EN (1 << 13) -#define OMAP3430_VP1_MAXVDD_EN (1 << 12) -#define OMAP3430_VP1_MINVDD_EN (1 << 11) -#define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10) -#define OMAP3430_IO_EN (1 << 9) -#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8) +#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25) +#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24) +#define OMAP3430_VC_RAERR_EN_MASK (1 << 23) +#define OMAP3430_VC_SAERR_EN_MASK (1 << 22) +#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21) +#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20) +#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19) +#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18) +#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17) +#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16) +#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15) +#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14) +#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13) +#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12) +#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11) +#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10) +#define OMAP3430_IO_EN_MASK (1 << 9) +#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8) #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 -#define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7) +#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7) #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 -#define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6) +#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6) #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 -#define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5) +#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5) #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 -#define OMAP3430_TRANSITION_EN (1 << 4) -#define OMAP3430_EVGENOFF_EN (1 << 3) -#define OMAP3430_EVGENON_EN (1 << 2) -#define OMAP3430_FS_USB_WKUP_EN (1 << 1) +#define OMAP3430_TRANSITION_EN_MASK (1 << 4) +#define OMAP3430_EVGENOFF_EN_MASK (1 << 3) +#define OMAP3430_EVGENON_EN_MASK (1 << 2) +#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1) /* RM_RSTST_MPU specific bits */ -#define OMAP3430_EMULATION_MPU_RST (1 << 11) +#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11) /* PM_WKDEP_MPU specific bits */ #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 @@ -289,7 +289,7 @@ #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) #define OMAP3430_ONLOADMODE_SHIFT 1 #define OMAP3430_ONLOADMODE_MASK (0x3 << 1) -#define OMAP3430_ENABLE (1 << 0) +#define OMAP3430_ENABLE_MASK (1 << 0) /* PM_EVGENONTIM_MPU */ #define OMAP3430_ONTIMEVAL_SHIFT 0 @@ -302,32 +302,32 @@ /* PM_PWSTCTRL_MPU specific bits */ #define OMAP3430_L2CACHEONSTATE_SHIFT 16 #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) -#define OMAP3430_L2CACHERETSTATE (1 << 8) -#define OMAP3430_LOGICL1CACHERETSTATE (1 << 2) +#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8) +#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2) /* PM_PWSTST_MPU specific bits */ #define OMAP3430_L2CACHESTATEST_SHIFT 6 #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) -#define OMAP3430_LOGICL1CACHESTATEST (1 << 2) +#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2) /* PM_PREPWSTST_MPU specific bits */ #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) -#define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2) +#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2) /* RM_RSTCTRL_CORE */ -#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1) -#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0) +#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) +#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) /* RM_RSTST_CORE specific bits */ -#define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10) -#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9) -#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8) +#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10) +#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9) +#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8) /* PM_WKEN1_CORE specific bits */ /* PM_MPUGRPSEL1_CORE specific bits */ -#define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5) +#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5) /* PM_IVA2GRPSEL1_CORE specific bits */ @@ -338,8 +338,8 @@ #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) #define OMAP3430_MEM1ONSTATE_SHIFT 16 #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) -#define OMAP3430_MEM2RETSTATE (1 << 9) -#define OMAP3430_MEM1RETSTATE (1 << 8) +#define OMAP3430_MEM2RETSTATE_MASK (1 << 9) +#define OMAP3430_MEM1RETSTATE_MASK (1 << 8) /* PM_PWSTST_CORE specific bits */ #define OMAP3430_MEM2STATEST_SHIFT 6 @@ -356,7 +356,7 @@ /* RM_RSTST_GFX specific bits */ /* PM_WKDEP_GFX specific bits */ -#define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2) +#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2) /* PM_PWSTCTRL_GFX specific bits */ @@ -365,33 +365,33 @@ /* PM_PREPWSTST_GFX specific bits */ /* PM_WKEN_WKUP specific bits */ -#define OMAP3430_EN_IO_CHAIN (1 << 16) -#define OMAP3430_EN_IO (1 << 8) -#define OMAP3430_EN_GPIO1 (1 << 3) +#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) +#define OMAP3430_EN_IO_MASK (1 << 8) +#define OMAP3430_EN_GPIO1_MASK (1 << 3) /* PM_MPUGRPSEL_WKUP specific bits */ /* PM_IVA2GRPSEL_WKUP specific bits */ /* PM_WKST_WKUP specific bits */ -#define OMAP3430_ST_IO_CHAIN (1 << 16) -#define OMAP3430_ST_IO (1 << 8) +#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) +#define OMAP3430_ST_IO_MASK (1 << 8) /* PRM_CLKSEL */ #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) /* PRM_CLKOUT_CTRL */ -#define OMAP3430_CLKOUT_EN (1 << 7) +#define OMAP3430_CLKOUT_EN_MASK (1 << 7) #define OMAP3430_CLKOUT_EN_SHIFT 7 /* RM_RSTST_DSS specific bits */ /* PM_WKEN_DSS */ -#define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0) +#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) /* PM_WKDEP_DSS specific bits */ -#define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2) +#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2) /* PM_PWSTCTRL_DSS specific bits */ @@ -402,7 +402,7 @@ /* RM_RSTST_CAM specific bits */ /* PM_WKDEP_CAM specific bits */ -#define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2) +#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2) /* PM_PWSTCTRL_CAM specific bits */ @@ -424,7 +424,7 @@ /* PM_WKST_PER specific bits */ /* PM_WKDEP_PER specific bits */ -#define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2) +#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2) /* PM_PWSTCTRL_PER specific bits */ @@ -467,26 +467,26 @@ /* PRM_VC_CMD_VAL_1 specific bits */ /* PRM_VC_CH_CONF */ -#define OMAP3430_CMD1 (1 << 20) -#define OMAP3430_RACEN1 (1 << 19) -#define OMAP3430_RAC1 (1 << 18) -#define OMAP3430_RAV1 (1 << 17) -#define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16) -#define OMAP3430_CMD0 (1 << 4) -#define OMAP3430_RACEN0 (1 << 3) -#define OMAP3430_RAC0 (1 << 2) -#define OMAP3430_RAV0 (1 << 1) -#define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0) +#define OMAP3430_CMD1_MASK (1 << 20) +#define OMAP3430_RACEN1_MASK (1 << 19) +#define OMAP3430_RAC1_MASK (1 << 18) +#define OMAP3430_RAV1_MASK (1 << 17) +#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16) +#define OMAP3430_CMD0_MASK (1 << 4) +#define OMAP3430_RACEN0_MASK (1 << 3) +#define OMAP3430_RAC0_MASK (1 << 2) +#define OMAP3430_RAV0_MASK (1 << 1) +#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0) /* PRM_VC_I2C_CFG */ -#define OMAP3430_HSMASTER (1 << 5) -#define OMAP3430_SREN (1 << 4) -#define OMAP3430_HSEN (1 << 3) +#define OMAP3430_HSMASTER_MASK (1 << 5) +#define OMAP3430_SREN_MASK (1 << 4) +#define OMAP3430_HSEN_MASK (1 << 3) #define OMAP3430_MCODE_SHIFT 0 #define OMAP3430_MCODE_MASK (0x7 << 0) /* PRM_VC_BYPASS_VAL */ -#define OMAP3430_VALID (1 << 24) +#define OMAP3430_VALID_MASK (1 << 24) #define OMAP3430_DATA_SHIFT 16 #define OMAP3430_DATA_MASK (0xff << 16) #define OMAP3430_REGADDR_SHIFT 8 @@ -495,8 +495,8 @@ #define OMAP3430_SLAVEADDR_MASK (0x7f << 0) /* PRM_RSTCTRL */ -#define OMAP3430_RST_DPLL3 (1 << 2) -#define OMAP3430_RST_GS (1 << 1) +#define OMAP3430_RST_DPLL3_MASK (1 << 2) +#define OMAP3430_RST_GS_MASK (1 << 1) /* PRM_RSTTIME */ #define OMAP3430_RSTTIME2_SHIFT 8 @@ -505,23 +505,23 @@ #define OMAP3430_RSTTIME1_MASK (0xff << 0) /* PRM_RSTST */ -#define OMAP3430_ICECRUSHER_RST (1 << 10) -#define OMAP3430_ICEPICK_RST (1 << 9) -#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8) -#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7) -#define OMAP3430_EXTERNAL_WARM_RST (1 << 6) -#define OMAP3430_SECURE_WD_RST (1 << 5) -#define OMAP3430_MPU_WD_RST (1 << 4) -#define OMAP3430_SECURITY_VIOL_RST (1 << 3) -#define OMAP3430_GLOBAL_SW_RST (1 << 1) -#define OMAP3430_GLOBAL_COLD_RST (1 << 0) +#define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) +#define OMAP3430_ICEPICK_RST_MASK (1 << 9) +#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) +#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) +#define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) +#define OMAP3430_SECURE_WD_RST_MASK (1 << 5) +#define OMAP3430_MPU_WD_RST_MASK (1 << 4) +#define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) +#define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) +#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) /* PRM_VOLTCTRL */ -#define OMAP3430_SEL_VMODE (1 << 4) -#define OMAP3430_SEL_OFF (1 << 3) -#define OMAP3430_AUTO_OFF (1 << 2) -#define OMAP3430_AUTO_RET (1 << 1) -#define OMAP3430_AUTO_SLEEP (1 << 0) +#define OMAP3430_SEL_VMODE_MASK (1 << 4) +#define OMAP3430_SEL_OFF_MASK (1 << 3) +#define OMAP3430_AUTO_OFF_MASK (1 << 2) +#define OMAP3430_AUTO_RET_MASK (1 << 1) +#define OMAP3430_AUTO_SLEEP_MASK (1 << 0) /* PRM_SRAM_PCHARGE */ #define OMAP3430_PCHARGE_TIME_SHIFT 0 @@ -550,10 +550,10 @@ #define OMAP3430_SETUP_TIME_MASK (0xffff << 0) /* PRM_POLCTRL */ -#define OMAP3430_OFFMODE_POL (1 << 3) -#define OMAP3430_CLKOUT_POL (1 << 2) -#define OMAP3430_CLKREQ_POL (1 << 1) -#define OMAP3430_EXTVOL_POL (1 << 0) +#define OMAP3430_OFFMODE_POL_MASK (1 << 3) +#define OMAP3430_CLKOUT_POL_MASK (1 << 2) +#define OMAP3430_CLKREQ_POL_MASK (1 << 1) +#define OMAP3430_EXTVOL_POL_MASK (1 << 0) /* PRM_VOLTSETUP2 */ #define OMAP3430_OFFMODESETUPTIME_SHIFT 0 |