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authorPaul Walmsley <paul@pwsan.com>2012-10-29 20:55:46 -0600
committerPaul Walmsley <paul@pwsan.com>2012-11-08 12:33:07 -0700
commitd08cce6a1d6952a7774e4b61066d469c16d47a11 (patch)
tree13b56e022d8c8eaf720256b0de9dd9e1460a5d18 /arch/arm/mach-omap2/prm2xxx.c
parentb6a4226c14001b0aa20b11c69190cb89d2237d3d (diff)
ARM: OMAP2/3: PRM: add SoC reset functions (using the CORE DPLL method)
Add SoC reset functions into the PRM code. These functions are based on code from mach-omap2/prcm.c. They reset the SoC using the CORE DPLL reset method (as opposed to one of the other two or three chip reset methods). Adding them here will facilitate their removal from arch/arm/mach-omap2/prcm.c. (prcm.c is deprecated.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/prm2xxx.c')
-rw-r--r--arch/arm/mach-omap2/prm2xxx.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index e2860f9c111..1f777bf2bc8 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -69,6 +69,20 @@ static u32 omap2xxx_prm_read_reset_sources(void)
return r;
}
+/**
+ * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
+ *
+ * Set the DPLL reset bit, which should reboot the SoC. This is the
+ * recommended way to restart the SoC. No return value.
+ */
+void omap2xxx_prm_dpll_reset(void)
+{
+ omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
+ OMAP2_RM_RSTCTRL);
+ /* OCP barrier */
+ omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
+}
+
int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
{
omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,