diff options
| author | Paul Walmsley <paul@pwsan.com> | 2009-05-28 14:03:59 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2009-05-28 14:03:59 -0700 |
| commit | 17a722caaef16835ab83f39046da1760cda8a578 (patch) | |
| tree | e8cf31c89edf38fae641ebbbdd427ad992bb18c2 /arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h | |
| parent | 2e12bd7ef175c9dc55dc215823b62a2247865012 (diff) | |
ARM: OMAP3: SDRC: add timing data for Qimonda HYB18M512160AF-6
Add timing data for the Qimonda HYB18M512160AF-6 SDRAM chip, used on
the OMAP3430SDP boards.
Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying
the chip used on 3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h')
| -rw-r--r-- | arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h new file mode 100644 index 00000000000..3751d293cb1 --- /dev/null +++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h @@ -0,0 +1,54 @@ +/* + * SDRC register values for the Qimonda HYB18M512160AF-6 + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * Copyright (C) 2008-2009 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 +#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 + +#include <mach/sdrc.h> + +/* Qimonda HYB18M512160AF-6 */ +static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = { + [0] = { + .rate = 166000000, + .actim_ctrla = 0x629db4c6, + .actim_ctrlb = 0x00012214, + .rfr_ctrl = 0x0004dc01, + .mr = 0x00000032, + }, + [1] = { + .rate = 165941176, + .actim_ctrla = 0x629db4c6, + .actim_ctrlb = 0x00012214, + .rfr_ctrl = 0x0004dc01, + .mr = 0x00000032, + }, + [2] = { + .rate = 83000000, + .actim_ctrla = 0x31512283, + .actim_ctrlb = 0x0001220a, + .rfr_ctrl = 0x00025501, + .mr = 0x00000022, + }, + [3] = { + .rate = 82970588, + .actim_ctrla = 0x31512283, + .actim_ctrlb = 0x0001220a, + .rfr_ctrl = 0x00025501, + .mr = 0x00000022, + }, + [4] = { + .rate = 0 + }, +}; + +#endif |