diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2009-05-28 14:16:04 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2009-05-28 14:16:04 -0700 |
| commit | 44169075e6eaa87bab6a296209d8d0610879b394 (patch) | |
| tree | 4aca7ea61215bb50d647476de30c558859c2f2f3 /arch/arm/mach-omap2/timer-gp.c | |
| parent | 7419045016e5002b3ccee72b28e41bf53dca68f2 (diff) | |
ARM: OMAP4: Add minimal support for omap4
This patch adds the support for OMAP4. The platform and machine specific
headers and sources updated for OMAP4430 SDP platform.
OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/timer-gp.c')
| -rw-r--r-- | arch/arm/mach-omap2/timer-gp.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index f36aba12090..2ce474a9d2b 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -17,9 +17,10 @@ * * Some parts based off of TI's 24xx code: * - * Copyright (C) 2004 Texas Instruments, Inc. + * Copyright (C) 2004-2009 Texas Instruments, Inc. * * Roughly modelled after the OMAP1 MPU timer code. + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -82,7 +83,8 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_PERIODIC: period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; period -= 1; - + if (cpu_is_omap44xx()) + period = 0xff; /* FIXME: */ omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); break; case CLOCK_EVT_MODE_ONESHOT: @@ -145,6 +147,9 @@ static void __init omap2_gp_clockevent_init(void) "timer-gp: omap_dm_timer_set_source() failed\n"); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); + if (cpu_is_omap44xx()) + /* Assuming 32kHz clk is driving GPT1 */ + tick_rate = 32768; /* FIXME: */ pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", gptimer_id, tick_rate); |