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authorTomi Valkeinen <tomi.valkeinen@ti.com>2013-10-09 16:12:37 +0300
committerPaul Walmsley <paul@pwsan.com>2013-10-24 09:06:44 -0600
commita861389a9f074d82081d0c7fbf30280a232c90d0 (patch)
tree0a8f2a9941d5f8f8064e45b757118ea56c35a3b2 /arch/arm/mach-omap2
parent272b98c6455f00884f0350f775c5342358ebb73f (diff)
ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can be configured without the need to get the parent of the fclk. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 1d5b5290d2a..a27a0af669a 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
OMAP4430_CM_DSS_DSS_CLKCTRL,
OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
+ CLK_SET_RATE_PARENT,
OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
0x0, NULL);