diff options
author | Thara Gopinath <thara@ti.com> | 2010-08-18 12:23:12 +0530 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-12-22 14:31:50 -0800 |
commit | b35cecf978e33bf8f4be0f36ffe00fe10f381c4a (patch) | |
tree | e64d7071a277931f9481761c1fa788994faab418 /arch/arm/mach-omap2 | |
parent | fb200cfb2330b959eabc94e2f2c15717ce8466af (diff) |
OMAP4: Smartreflex framework extensions
This patch extends the smartreflex framework to support
OMAP4. The changes are minor like compiling smartreflex Kconfig
option for OMAP4 also, and a couple of OMAP4 checks in
the smartreflex framework.
The change in sr_device.c where new logic has to be introduced
for reading the efuse registers is due to the fact that in OMAP4
the efuse registers are 24 bit aligned. A __raw_readl will
fail for non-32 bit aligned address and hence the 8-bit read
and shift.
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/smartreflex.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-omap2/sr_device.c | 17 |
2 files changed, 22 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 52a05b336c0..77ecebf3fae 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -153,7 +153,11 @@ static void sr_set_clk_length(struct omap_sr *sr) struct clk *sys_ck; u32 sys_clk_speed; - sys_ck = clk_get(NULL, "sys_ck"); + if (cpu_is_omap34xx()) + sys_ck = clk_get(NULL, "sys_ck"); + else + sys_ck = clk_get(NULL, "sys_clkin_ck"); + if (IS_ERR(sys_ck)) { dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n", __func__); @@ -193,7 +197,7 @@ static void sr_set_regfields(struct omap_sr *sr) * file or pmic specific data structure. In that case these structure * fields will have to be populated using the pdata or pmic structure. */ - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { sr->err_weight = OMAP3430_SR_ERRWEIGHT; sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT; sr->accum_data = OMAP3430_SR_ACCUMDATA; diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 9a3538fb633..786d685c09a 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -20,6 +20,7 @@ #include <linux/err.h> #include <linux/slab.h> +#include <linux/io.h> #include <plat/omap_device.h> #include <plat/smartreflex.h> @@ -51,7 +52,21 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data, GFP_KERNEL); for (i = 0; i < count; i++) { - u32 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs); + u32 v; + /* + * In OMAP4 the efuse registers are 24 bit aligned. + * A __raw_readl will fail for non-32 bit aligned address + * and hence the 8-bit read and shift. + */ + if (cpu_is_omap44xx()) { + u16 offset = volt_data[i].sr_efuse_offs; + + v = omap_ctrl_readb(offset) | + omap_ctrl_readb(offset + 1) << 8 | + omap_ctrl_readb(offset + 2) << 16; + } else { + v = omap_ctrl_readl(volt_data[i].sr_efuse_offs); + } nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs; nvalue_table[i].nvalue = v; |