diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-10-04 22:57:00 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-10-04 22:57:51 +0200 |
| commit | c37d6154c0b9163c27e53cc1d0be3867b4abd760 (patch) | |
| tree | 7a24522c56d1cb284dff1d3c225bbdaba0901bb5 /arch/arm/mach-omap2 | |
| parent | e7a570ff7dff9af6e54ff5e580a61ec7652137a0 (diff) | |
| parent | 8a1ab3155c2ac7fbe5f2038d6e26efeb607a1498 (diff) | |
Merge branch 'disintegrate-asm-generic' of git://git.infradead.org/users/dhowells/linux-headers into asm-generic
Patches from David Howells <dhowells@redhat.com>:
This is to complete part of the UAPI disintegration for which the
preparatory patches were pulled recently.
Note that there are some fixup patches which are at the base of the
branch aimed at you, plus all arches get the asm-generic branch merged in too.
* 'disintegrate-asm-generic' of git://git.infradead.org/users/dhowells/linux-headers:
UAPI: (Scripted) Disintegrate include/asm-generic
UAPI: Fix conditional header installation handling (notably kvm_para.h on m68k)
c6x: remove c6x signal.h
UAPI: Split compound conditionals containing __KERNEL__ in Arm64
UAPI: Fix the guards on various asm/unistd.h files
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-omap2')
165 files changed, 5191 insertions, 2170 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 346fd26f3aa..a6219eaf1f6 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -18,12 +18,16 @@ config ARCH_OMAP2PLUS_TYPICAL select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 select HIGHMEM + select PINCTRL help Compile a kernel suitable for booting most boards config SOC_HAS_OMAP2_SDRC bool "OMAP2 SDRAM Controller support" +config SOC_HAS_REALTIME_COUNTER + bool "Real time free running counter" + config ARCH_OMAP2 bool "TI OMAP2" depends on ARCH_OMAP2PLUS @@ -44,6 +48,7 @@ config ARCH_OMAP3 select ARM_CPU_SUSPEND if PM select MULTI_IRQ_HANDLER select SOC_HAS_OMAP2_SDRC + select OMAP_INTERCONNECT config ARCH_OMAP4 bool "TI OMAP4" @@ -63,6 +68,7 @@ config ARCH_OMAP4 select USB_ARCH_HAS_EHCI if USB_SUPPORT select ARM_CPU_SUSPEND if PM select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP + select OMAP_INTERCONNECT config SOC_OMAP5 bool "TI OMAP5" @@ -70,6 +76,8 @@ config SOC_OMAP5 select ARM_GIC select HAVE_SMP select ARM_CPU_SUSPEND if PM + select SOC_HAS_REALTIME_COUNTER + select ARM_ARCH_TIMER comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 34c2c7f59f0..7d6abda3b74 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -4,36 +4,30 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ - common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o + common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o -omap-2-3-common = irq.o -hwmod-common = omap_hwmod.o \ - omap_hwmod_common_data.o -clock-common = clock.o clock_common_data.o \ - clkt_dpll.o clkt_clksel.o -secure-common = omap-smc.o omap-secure.o +# INTCPS IP block support - XXX should be moved to drivers/ +obj-$(CONFIG_ARCH_OMAP2) += irq.o +obj-$(CONFIG_ARCH_OMAP3) += irq.o +obj-$(CONFIG_SOC_AM33XX) += irq.o -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) -obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) -obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) -obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) +# Secure monitor API support +obj-$(CONFIG_ARCH_OMAP3) += omap-smc.o omap-secure.o +obj-$(CONFIG_ARCH_OMAP4) += omap-smc.o omap-secure.o +obj-$(CONFIG_SOC_OMAP5) += omap-smc.o omap-secure.o ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o endif -obj-$(CONFIG_TWL4030_CORE) += omap_twl.o -obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o +obj-$(CONFIG_TWL4030_CORE) += omap_twl.o # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -omap-4-5-common = omap4-common.o omap-wakeupgen.o \ - sleep44xx.o -obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) -obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) +obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o +obj-$(CONFIG_SOC_OMAP5) += omap4-common.o omap-wakeupgen.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -58,6 +52,7 @@ obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o +obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o # OPP table initialization ifeq ($(CONFIG_PM_OPP),y) @@ -68,15 +63,15 @@ endif # Power Management ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o +obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o -obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o +obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o +obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o sleep44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o -obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o +obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) @@ -88,92 +83,76 @@ endif endif ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o +obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o endif # PRCM -omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \ - prcm_mpu44xx.o prminst44xx.o \ - vc44xx_data.o vp44xx_data.o -obj-y += prm_common.o -obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-y += prcm.o prm_common.o +obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o -obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o -obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o +obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o +omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ + prcm_mpu44xx.o prminst44xx.o \ + vc44xx_data.o vp44xx_data.o \ + prm44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) # OMAP voltage domains -voltagedomain-common := voltage.o vc.o vp.o -obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) +obj-y += voltage.o vc.o vp.o obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) -obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) +obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o # OMAP powerdomain framework -powerdomain-common += powerdomain.o powerdomain-common.o -obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) +obj-y += powerdomain.o powerdomain-common.o obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o # PRCM clockdomain control -clockdomain-common += clockdomain.o -obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) +obj-y += clockdomain.o obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o # Clock framework -obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o +obj-y += clock.o clock_common_data.o \ + clkt_dpll.o clkt_clksel.o +obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o clkt2xxx_sys.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o +obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o clkt_iclk.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o -obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o +obj-$(CONFIG_ARCH_OMAP4) += clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o -obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o -obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(clock-common) +obj-$(CONFIG_SOC_AM33XX) += dpll3xxx.o clock33xx_data.o obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) @@ -181,6 +160,7 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data +obj-y += omap_hwmod_common_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o @@ -194,16 +174,12 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o +obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o -# L3 interconnect -obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o -obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o -obj-$(CONFIG_SOC_OMAP5) += omap_l3_noc.o - obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o @@ -229,10 +205,10 @@ obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o -obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o +obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o obj-$(CONFIG_MACH_OVERO) += board-overo.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h new file mode 100644 index 00000000000..06c19bb7bca --- /dev/null +++ b/arch/arm/mach-omap2/am33xx.h @@ -0,0 +1,25 @@ +/* + * This file contains the address info for various AM33XX modules. + * + * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_AM33XX_H +#define __ASM_ARCH_AM33XX_H + +#define L4_SLOW_AM33XX_BASE 0x48000000 + +#define AM33XX_SCM_BASE 0x44E10000 +#define AM33XX_CTRL_BASE AM33XX_SCM_BASE +#define AM33XX_PRCM_BASE 0x44E00000 + +#endif /* __ASM_ARCH_AM33XX_H */ diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c index 2c90ac68668..d0c54c573d3 100644 --- a/arch/arm/mach-omap2/am35xx-emac.c +++ b/arch/arm/mach-omap2/am35xx-emac.c @@ -19,7 +19,7 @@ #include <linux/davinci_emac.h> #include <asm/system.h> #include <plat/omap_device.h> -#include <mach/am35xx.h> +#include "am35xx.h" #include "control.h" #include "am35xx-emac.h" diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/am35xx.h index 95594495fcf..95594495fcf 100644 --- a/arch/arm/mach-omap2/include/mach/am35xx.h +++ b/arch/arm/mach-omap2/am35xx.h diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 9511584fdc4..95b384d54f8 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -33,11 +33,10 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> #include <plat/usb.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> @@ -212,9 +211,6 @@ static struct regulator_init_data sdp2430_vmmc1 = { }; static struct twl4030_gpio_platform_data sdp2430_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, }; static struct twl4030_platform_data sdp2430_twldata = { @@ -235,7 +231,7 @@ static int __init omap2430_i2c_init(void) sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78); omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, ARRAY_SIZE(sdp2430_i2c1_boardinfo)); - omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ, + omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START, &sdp2430_twldata); return 0; } diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index a98c688058a..96cd3693e1a 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -24,14 +24,12 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/mmc/host.h> +#include <linux/platform_data/spi-omap2-mcspi.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mcspi.h> -#include <plat/board.h> #include <plat/usb.h> #include "common.h" #include <plat/dma.h> @@ -39,7 +37,7 @@ #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" #include "board-flash.h" #include "mux.h" @@ -191,9 +189,6 @@ static struct omap_dss_board_info sdp3430_dss_data = { .default_device = &sdp3430_lcd_device, }; -static struct omap_board_config_kernel sdp3430_config[] __initdata = { -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -233,9 +228,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data sdp3430_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13) | BIT(16) | BIT(17), .setup = sdp3430_twl_gpio_setup, @@ -576,8 +568,6 @@ static void __init omap_3430sdp_init(void) int gpio_pendown; omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_board_config = sdp3430_config; - omap_board_config_size = ARRAY_SIZE(sdp3430_config); omap_hsmmc_init(mmc); omap3430_i2c_init(); omap_display_init(&sdp3430_dss_data); diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 2dc9ba523c7..fc224ad8674 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -17,8 +17,7 @@ #include <asm/mach/arch.h> #include "common.h" -#include <plat/board.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" #include <plat/usb.h> #include <mach/board-zoom.h> @@ -67,9 +66,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = { .reset_gpio_port[2] = -EINVAL }; -static struct omap_board_config_kernel sdp_config[] __initdata = { -}; - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, @@ -197,8 +193,6 @@ static struct flash_partitions sdp_flash_partitions[] = { static void __init omap_sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); - omap_board_config = sdp_config; - omap_board_config_size = ARRAY_SIZE(sdp_config); zoom_peripherals_init(); omap_sdrc_init(h8mbx00u0mer0em_sdrc_params, h8mbx00u0mer0em_sdrc_params); diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index ad8a7d94afc..a88809a59ea 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -28,23 +28,22 @@ #include <linux/leds_pwm.h> #include <linux/platform_data/omap4-keypad.h> -#include <mach/hardware.h> #include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> #include <plat/mmc.h> -#include <plat/omap4-keypad.h> +#include "omap4-keypad.h" #include <video/omapdss.h> #include <video/omap-panel-nokia-dsi.h> #include <video/omap-panel-picodlp.h> #include <linux/wl12xx.h> #include <linux/platform_data/omap-abe-twl6040.h> +#include "soc.h" #include "mux.h" #include "hsmmc.h" #include "control.h" @@ -544,7 +543,14 @@ static struct twl6040_platform_data twl6040_data = { .codec = &twl6040_codec, .vibra = &twl6040_vibra, .audpwron_gpio = 127, - .irq_base = TWL6040_CODEC_IRQ_BASE, +}; + +static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = { + { + I2C_BOARD_INFO("twl6040", 0x4b), + .irq = 119 + OMAP44XX_IRQ_GIC_START, + .platform_data = &twl6040_data, + }, }; static struct twl4030_platform_data sdp4430_twldata = { @@ -580,8 +586,8 @@ static int __init omap4_i2c_init(void) TWL_COMMON_REGULATOR_CLK32KG | TWL_COMMON_REGULATOR_V1V8 | TWL_COMMON_REGULATOR_V2V1); - omap4_pmic_init("twl6030", &sdp4430_twldata, - &twl6040_data, OMAP44XX_IRQ_SYS_2N); + omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo, + ARRAY_SIZE(sdp4430_i2c_1_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); @@ -909,6 +915,7 @@ static void __init omap_4430sdp_init(void) MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ .atag_offset = 0x100, + .smp = smp_ops(omap4_smp_ops), .reserve = omap_reserve, .map_io = omap4_map_io, .init_early = omap4430_init_early, diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 92432c28673..318feadb1d6 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -21,12 +21,10 @@ #include <linux/init.h> #include <linux/gpio.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> @@ -37,11 +35,6 @@ #define GPIO_USB_POWER 35 #define GPIO_USB_NRESET 38 - -/* Board initialization */ -static struct omap_board_config_kernel am3517_crane_config[] __initdata = { -}; - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, @@ -67,9 +60,6 @@ static void __init am3517_crane_init(void) omap_serial_init(); omap_sdrc_init(NULL, NULL); - omap_board_config = am3517_crane_config; - omap_board_config_size = ARRAY_SIZE(am3517_crane_config); - /* Configure GPIO for EHCI port */ if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 18f601096ce..0d99c9110d0 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -25,14 +25,13 @@ #include <linux/can/platform/ti_hecc.h> #include <linux/davinci_emac.h> #include <linux/mmc/host.h> +#include <linux/platform_data/gpio-omap.h> -#include <mach/hardware.h> -#include <mach/am35xx.h> +#include "am35xx.h" #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> #include <video/omapdss.h> @@ -296,8 +295,7 @@ static struct resource am3517_hecc_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_35XX_HECC0_IRQ, - .end = INT_35XX_HECC0_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }, }; @@ -324,9 +322,6 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata) platform_device_register(&am3517_hecc_device); } -static struct omap_board_config_kernel am3517_evm_config[] __initdata = { -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -346,8 +341,6 @@ static struct omap2_hsmmc_info mmc[] = { static void __init am3517_evm_init(void) { - omap_board_config = am3517_evm_config; - omap_board_config_size = ARRAY_SIZE(am3517_evm_config); omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); am3517_evm_i2c_init(); diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index e5fa46bfde2..3e2d76f05af 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -29,13 +29,11 @@ #include <linux/smc91x.h> #include <linux/gpio.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <plat/led.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 97d719047af..8ffd612c5e0 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -23,6 +23,7 @@ #include <linux/input/matrix_keypad.h> #include <linux/delay.h> #include <linux/gpio.h> +#include <linux/platform_data/gpio-omap.h> #include <linux/i2c/at24.h> #include <linux/i2c/twl.h> @@ -37,15 +38,14 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/gpmc.h> #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <mach/hardware.h> @@ -64,7 +64,7 @@ #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include <linux/smsc911x.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = { .id = 0, @@ -470,9 +470,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, } static struct twl4030_gpio_platform_data cm_t35_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .setup = cm_t35_twl_gpio_setup, }; @@ -714,13 +711,8 @@ static inline void cm_t35_init_mux(void) {} static inline void cm_t3730_init_mux(void) {} #endif -static struct omap_board_config_kernel cm_t35_config[] __initdata = { -}; - static void __init cm_t3x_common_init(void) { - omap_board_config = cm_t35_config; - omap_board_config_size = ARRAY_SIZE(cm_t35_config); omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index a33ad4641d9..59c0a45f75b 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -38,13 +38,12 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/gpmc.h> -#include <mach/am35xx.h> +#include "am35xx.h" #include "mux.h" #include "control.h" @@ -90,8 +89,7 @@ static struct resource cm_t3517_hecc_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_35XX_HECC0_IRQ, - .end = INT_35XX_HECC0_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }, }; @@ -249,9 +247,6 @@ static void __init cm_t3517_init_nand(void) static inline void cm_t3517_init_nand(void) {} #endif -static struct omap_board_config_kernel cm_t3517_config[] __initdata = { -}; - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { /* GPIO186 - Green LED */ @@ -285,8 +280,6 @@ static void __init cm_t3517_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); omap_sdrc_init(NULL, NULL); - omap_board_config = cm_t3517_config; - omap_board_config_size = ARRAY_SIZE(cm_t3517_config); cm_t3517_init_leds(); cm_t3517_init_nand(); cm_t3517_init_rtc(); diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 6567c1cd557..7bb8056d438 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -32,31 +32,27 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> - -#include <mach/hardware.h> -#include <mach/id.h> +#include "id.h" #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> #include <linux/dm9000.h> #include <linux/interrupt.h> #include "sdram-micron-mt46h32m32lf-6.h" - #include "mux.h" #include "hsmmc.h" #include "common-board-devices.h" @@ -236,9 +232,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data devkit8000_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .pulldowns = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13) | BIT(15) | BIT(16) | BIT(17), diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 53c39d239d6..0cabe61cd50 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -16,13 +16,14 @@ #include <linux/platform_device.h> #include <linux/mtd/physmap.h> #include <linux/io.h> -#include <plat/irqs.h> +#include <plat/cpu.h> #include <plat/gpmc.h> -#include <plat/nand.h> -#include <plat/onenand.h> +#include <linux/platform_data/mtd-nand-omap2.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include <plat/tc.h> +#include "common.h" #include "board-flash.h" #define REG_FPGA_REV 0x10 @@ -140,7 +141,6 @@ __init board_nand_init(struct mtd_partition *nand_parts, board_nand_data.devsize = nand_type; board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; - board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; gpmc_nand_init(&board_nand_data); } #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 6f93a20536e..601ecdfb1cf 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -16,11 +16,9 @@ #include <linux/of_platform.h> #include <linux/irqdomain.h> -#include <mach/hardware.h> #include <asm/hardware/gic.h> #include <asm/mach/arch.h> -#include <plat/board.h> #include "common.h" #include "common-board-devices.h" @@ -127,6 +125,7 @@ static const char *omap4_boards_compat[] __initdata = { DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") .reserve = omap_reserve, + .smp = smp_ops(omap4_smp_ops), .map_io = omap4_map_io, .init_early = omap4430_init_early, .init_irq = omap_gic_of_init, @@ -147,6 +146,7 @@ static const char *omap5_boards_compat[] __initdata = { DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)") .reserve = omap_reserve, + .smp = smp_ops(omap4_smp_ops), .map_io = omap5_map_io, .init_early = omap5_init_early, .init_irq = omap_gic_of_init, diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index ace20482e3e..f6c48dd764f 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -27,20 +27,19 @@ #include <linux/io.h> #include <linux/input/matrix_keypad.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> -#include "common.h" #include <plat/menelaus.h> #include <plat/dma.h> #include <plat/gpmc.h> +#include "debug-devices.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> +#include "common.h" #include "mux.h" #include "control.h" diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 28214483aab..fb8bd837dd1 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -29,13 +29,13 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> #include <plat/usb.h> + #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> -#include <plat/onenand.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include "mux.h" #include "hsmmc.h" @@ -192,7 +192,7 @@ static void __init igep_flash_init(void) {} #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include <linux/smsc911x.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct omap_smsc911x_platform_data smsc911x_cfg = { .cs = IGEP2_SMSC911X_CS, @@ -425,9 +425,6 @@ static int igep_twl_gpio_setup(struct device *dev, }; static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .setup = igep_twl_gpio_setup, }; diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index ef9e8297749..ee8c3cfb95b 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -28,21 +28,17 @@ #include <linux/io.h> #include <linux/smsc911x.h> #include <linux/mmc/host.h> +#include <linux/platform_data/spi-omap2-mcspi.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mcspi.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> #include <mach/board-zoom.h> - -#include <asm/delay.h> #include <plat/usb.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> @@ -275,9 +271,6 @@ static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) } static struct twl4030_gpio_platform_data ldp_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .setup = ldp_twl_gpio_setup, }; diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 677357ff61a..d95f727ca39 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -20,19 +20,16 @@ #include <linux/i2c.h> #include <linux/spi/spi.h> #include <linux/usb/musb.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include <sound/tlv320aic3x.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> -#include <plat/board.h> #include "common.h" #include <plat/menelaus.h> -#include <mach/irqs.h> -#include <plat/mcspi.h> -#include <plat/onenand.h> #include <plat/mmc.h> -#include <plat/serial.h> #include "mux.h" @@ -553,8 +550,8 @@ static int n8x0_auto_sleep_regulators(void) ret = menelaus_set_regulator_sleep(1, val); if (ret < 0) { - printk(KERN_ERR "Could not set regulators to sleep on " - "menelaus: %u\n", ret); + pr_err("Could not set regulators to sleep on menelaus: %u\n", + ret); return ret; } return 0; @@ -566,8 +563,7 @@ static int n8x0_auto_voltage_scale(void) ret = menelaus_set_vcore_hw(1400, 1050); if (ret < 0) { - printk(KERN_ERR "Could not set VCORE voltage on " - "menelaus: %u\n", ret); + pr_err("Could not set VCORE voltage on menelaus: %u\n", ret); return ret; } return 0; @@ -600,7 +596,7 @@ static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { { I2C_BOARD_INFO("menelaus", 0x72), - .irq = INT_24XX_SYS_NIRQ, + .irq = 7 + OMAP_INTC_START, .platform_data = &n8x0_menelaus_platform_data, }, }; diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 6202fc76e49..68ff8d51973 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -33,18 +33,16 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <plat/board.h> #include "common.h" #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> #include <plat/gpmc.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/usb.h> #include <plat/omap_device.h> @@ -297,9 +295,6 @@ static int beagle_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data beagle_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .pullups = BIT(1), .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 0d362e9f9cb..c64e565bdef 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -32,6 +32,7 @@ #include <linux/spi/ads7846.h> #include <linux/i2c/twl.h> #include <linux/usb/otg.h> +#include <linux/usb/nop-usb-xceiv.h> #include <linux/smsc911x.h> #include <linux/wl12xx.h> @@ -40,16 +41,14 @@ #include <linux/mmc/host.h> #include <linux/export.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include <plat/usb.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include "common.h" -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> @@ -75,6 +74,18 @@ #define OMAP3EVM_GEN1_ETHR_GPIO_RST 64 #define OMAP3EVM_GEN2_ETHR_GPIO_RST 7 +/* + * OMAP35x EVM revision + * Run time detection of EVM revision is done by reading Ethernet + * PHY ID - + * GEN_1 = 0x01150000 + * GEN_2 = 0x92200000 + */ +enum { + OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */ + OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */ +}; + static u8 omap3_evm_version; u8 get_omap3_evm_rev(void) @@ -108,7 +119,7 @@ static void __init omap3_evm_get_revision(void) } #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct omap_smsc911x_platform_data smsc911x_cfg = { .cs = OMAP3EVM_SMSC911X_CS, @@ -377,9 +388,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data omap3evm_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .setup = omap3evm_twl_gpio_setup, }; @@ -526,9 +534,6 @@ static int __init omap3_evm_i2c_init(void) return 0; } -static struct omap_board_config_kernel omap3_evm_config[] __initdata = { -}; - static struct usbhs_omap_board_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, @@ -688,9 +693,6 @@ static void __init omap3_evm_init(void) obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux; omap3_mux_init(obm, OMAP_PACKAGE_CBB); - omap_board_config = omap3_evm_config; - omap_board_config_size = ARRAY_SIZE(omap3_evm_config); - omap_mux_init_gpio(63, OMAP_PIN_INPUT); omap_hsmmc_init(mmc); diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index fca93d1afd4..7bd8253b5d1 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -30,24 +30,21 @@ #include <linux/i2c/twl.h> #include <linux/mmc/host.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include "gpmc-smsc911x.h" +#include <plat/gpmc.h> +#include <plat/sdrc.h> +#include <plat/usb.h> + +#include "common.h" #include "mux.h" #include "hsmmc.h" #include "control.h" #include "common-board-devices.h" -#include <plat/mux.h> -#include <plat/board.h> -#include "common.h" -#include <plat/gpmc-smsc911x.h> -#include <plat/gpmc.h> -#include <plat/sdrc.h> -#include <plat/usb.h> - #define OMAP3LOGIC_SMSC911X_CS 1 #define OMAP3530_LV_SOM_MMC_GPIO_CD 110 @@ -78,9 +75,6 @@ static struct regulator_init_data omap3logic_vmmc1 = { }; static struct twl4030_gpio_platform_data omap3logic_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .pullups = BIT(1), .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 57aebee44fd..00a1f4ae6e4 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -35,18 +35,16 @@ #include <linux/mmc/host.h> #include <linux/mmc/card.h> #include <linux/regulator/fixed.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" -#include <mach/hardware.h> -#include <plat/mcspi.h> #include <plat/usb.h> #include <video/omapdss.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" @@ -321,9 +319,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .setup = omap3pandora_twl_gpio_setup, }; diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index b318f5602e3..c7f3d026e6d 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -28,23 +28,26 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> #include <linux/mmc/host.h> +#include <linux/input/matrix_keypad.h> +#include <linux/spi/spi.h> +#include <linux/interrupt.h> +#include <linux/smsc911x.h> +#include <linux/i2c/at24.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> #include <linux/interrupt.h> @@ -57,7 +60,7 @@ #include "common-board-devices.h" #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" #define OMAP3STALKER_ETHR_START 0x2c000000 #define OMAP3STALKER_ETHR_SIZE 1024 @@ -279,9 +282,6 @@ omap3stalker_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data omap3stalker_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .setup = omap3stalker_twl_gpio_setup, }; @@ -362,9 +362,6 @@ static int __init omap3_stalker_i2c_init(void) #define OMAP3_STALKER_TS_GPIO 175 -static struct omap_board_config_kernel omap3_stalker_config[] __initdata = { -}; - static struct platform_device *omap3_stalker_devices[] __initdata = { &keys_gpio, }; @@ -399,8 +396,6 @@ static void __init omap3_stalker_init(void) { regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); - omap_board_config = omap3_stalker_config; - omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); omap_mux_init_gpio(23, OMAP_PIN_INPUT); omap_hsmmc_init(mmc); diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 485d14d6a8c..944ffc43657 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -29,7 +29,7 @@ #include <linux/mtd/nand.h> #include <linux/mmc/host.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> @@ -37,17 +37,15 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> #include <asm/system_info.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/usb.h> #include "mux.h" @@ -139,9 +137,6 @@ static int touchbook_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data touchbook_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .pullups = BIT(1), .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 70f6d1d2546..e0dd70b9d91 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -32,19 +32,18 @@ #include <linux/wl12xx.h> #include <linux/platform_data/omap-abe-twl6040.h> -#include <mach/hardware.h> #include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <video/omapdss.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> #include <plat/mmc.h> #include <video/omap-panel-tfp410.h> +#include "soc.h" #include "hsmmc.h" #include "control.h" #include "mux.h" @@ -263,7 +262,14 @@ static struct twl6040_codec_data twl6040_codec = { static struct twl6040_platform_data twl6040_data = { .codec = &twl6040_codec, .audpwron_gpio = 127, - .irq_base = TWL6040_CODEC_IRQ_BASE, +}; + +static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = { + { + I2C_BOARD_INFO("twl6040", 0x4b), + .irq = 119 + OMAP44XX_IRQ_GIC_START, + .platform_data = &twl6040_data, + }, }; /* Panda board uses the common PMIC configuration */ @@ -293,8 +299,8 @@ static int __init omap4_panda_i2c_init(void) TWL_COMMON_REGULATOR_CLK32KG | TWL_COMMON_REGULATOR_V1V8 | TWL_COMMON_REGULATOR_V2V1); - omap4_pmic_init("twl6030", &omap4_panda_twldata, - &twl6040_data, OMAP44XX_IRQ_SYS_2N); + omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo, + ARRAY_SIZE(panda_i2c_1_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); /* * Bus 3 is attached to the DVI port where devices like the pico DLP @@ -518,6 +524,7 @@ static void __init omap4_panda_init(void) MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") /* Maintainer: David Anders - Texas Instruments Inc */ .atag_offset = 0x100, + .smp = smp_ops(omap4_smp_ops), .reserve = omap_reserve, .map_io = omap4_map_io, .init_early = omap4430_init_early, diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 779734d8ba3..2e7f24030fc 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -37,21 +37,19 @@ #include <linux/mtd/partitions.h> #include <linux/mmc/host.h> +#include <linux/platform_data/mtd-nand-omap2.h> +#include <linux/platform_data/spi-omap2-mcspi.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> #include <plat/gpmc.h> -#include <mach/hardware.h> -#include <plat/nand.h> -#include <plat/mcspi.h> -#include <plat/mux.h> #include <plat/usb.h> #include "mux.h" @@ -116,7 +114,7 @@ static inline void __init overo_ads7846_init(void) { return; } #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include <linux/smsc911x.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct omap_smsc911x_platform_data smsc911x_cfg = { .id = 0, @@ -399,9 +397,6 @@ static int overo_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data overo_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .setup = overo_twl_gpio_setup, }; @@ -522,8 +517,7 @@ static void __init overo_init(void) udelay(10); gpio_set_value(OVERO_GPIO_W2W_NRESET, 1); } else { - printk(KERN_ERR "could not obtain gpio for " - "OVERO_GPIO_W2W_NRESET\n"); + pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n"); } ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios)); @@ -542,8 +536,7 @@ static void __init overo_init(void) if (ret == 0) gpio_export(OVERO_GPIO_USBH_CPEN, 0); else - printk(KERN_ERR "could not obtain gpio for " - "OVERO_GPIO_USBH_CPEN\n"); + pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n"); } MACHINE_START(OVERO, "Gumstix Overo") diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c index 0ad1bb3bdb9..45997bfbcbd 100644 --- a/arch/arm/mach-omap2/board-rm680.c +++ b/arch/arm/mach-omap2/board-rm680.c @@ -17,6 +17,7 @@ #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> #include <linux/regulator/consumer.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -26,7 +27,7 @@ #include <plat/usb.h> #include <plat/gpmc.h> #include "common.h" -#include <plat/onenand.h> +#include <plat/serial.h> #include "mux.h" #include "hsmmc.h" @@ -72,9 +73,6 @@ static struct platform_device *rm680_peripherals_devices[] __initdata = { /* TWL */ static struct twl4030_gpio_platform_data rm680_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .pullups = BIT(0), .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15), }; @@ -87,7 +85,7 @@ static struct twl4030_platform_data rm680_twl_data = { static void __init rm680_i2c_init(void) { omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0); - omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data); + omap_pmic_init(1, 2900, "twl5031", 7 + OMAP_INTC_START, &rm680_twl_data); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, NULL, 0); } diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index df2534de336..3945c501708 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -25,17 +25,17 @@ #include <linux/gpio_keys.h> #include <linux/mmc/host.h> #include <linux/power/isp1704_charger.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/mtd-onenand-omap2.h> + #include <asm/system_info.h> -#include <plat/mcspi.h> -#include <plat/board.h> #include "common.h" #include <plat/dma.h> #include <plat/gpmc.h> -#include <plat/onenand.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" -#include <mach/board-rx51.h> +#include "board-rx51.h" #include <sound/tlv320aic3x.h> #include <sound/tpa6130a2-plat.h> @@ -774,9 +774,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) } static struct twl4030_gpio_platform_data rx51_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(9) | BIT(10) | BIT(11) @@ -1051,7 +1048,7 @@ static int __init rx51_i2c_init(void) rx51_twldata.vdac->constraints.apply_uV = true; rx51_twldata.vdac->constraints.name = "VDAC"; - omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata); + omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata); omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2, ARRAY_SIZE(rx51_peripherals_i2c_board_info_2)); #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE) diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index 2c1289bd5e6..c22e111bcd0 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -17,9 +17,9 @@ #include <asm/mach-types.h> #include <video/omapdss.h> #include <plat/vram.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> -#include <mach/board-rx51.h> +#include "board-rx51.h" #include "mux.h" diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 345dd931f76..7bbb05d9689 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -17,14 +17,12 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/leds.h> +#include <linux/platform_data/spi-omap2-mcspi.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mcspi.h> -#include <plat/board.h> #include "common.h" #include <plat/dma.h> #include <plat/gpmc.h> diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/board-rx51.h index b76f49e7eed..b76f49e7eed 100644 --- a/arch/arm/mach-omap2/include/mach/board-rx51.h +++ b/arch/arm/mach-omap2/board-rx51.h diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c index d4c8392cadb..c4f8833b4c3 100644 --- a/arch/arm/mach-omap2/board-ti8168evm.c +++ b/arch/arm/mach-omap2/board-ti8168evm.c @@ -15,13 +15,10 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/irqs.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> @@ -32,15 +29,10 @@ static struct omap_musb_board_data musb_board_data = { .power = 500, }; -static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = { -}; - static void __init ti81xx_evm_init(void) { omap_serial_init(); omap_sdrc_init(NULL, NULL); - omap_board_config = ti81xx_evm_config; - omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config); usb_musb_init(&musb_board_data); } diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c index f64f4417306..afb2278a29f 100644 --- a/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -18,10 +18,13 @@ #include <linux/regulator/machine.h> #include <plat/gpmc.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" #include <mach/board-zoom.h> +#include "soc.h" +#include "common.h" + #define ZOOM_SMSC911X_CS 7 #define ZOOM_SMSC911X_GPIO 158 #define ZOOM_QUADUART_CS 3 @@ -81,8 +84,7 @@ static inline void __init zoom_init_quaduart(void) quart_cs = ZOOM_QUADUART_CS; if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) { - printk(KERN_ERR "Failed to request GPMC mem" - "for Quad UART(TL16CP754C)\n"); + pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n"); return; } @@ -104,8 +106,8 @@ static inline int omap_zoom_debugboard_detect(void) if (gpio_request_one(debug_board_detect, GPIOF_IN, "Zoom debug board detect") < 0) { - printk(KERN_ERR "Failed to request GPIO%d for Zoom debug" - "board detect\n", debug_board_detect); + pr_err("Failed to request GPIO%d for Zoom debug board detect\n", + debug_board_detect); return 0; } diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index 28187f134ff..b940ab2259f 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -14,10 +14,12 @@ #include <linux/gpio.h> #include <linux/i2c/twl.h> #include <linux/spi/spi.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <video/omapdss.h> #include <mach/board-zoom.h> +#include "common.h" + #define LCD_PANEL_RESET_GPIO_PROD 96 #define LCD_PANEL_RESET_GPIO_PILOT 55 #define LCD_PANEL_QVGA_GPIO 56 diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index b797cb27961..6bcc107b9fc 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -19,6 +19,7 @@ #include <linux/regulator/fixed.h> #include <linux/wl12xx.h> #include <linux/mmc/host.h> +#include <linux/platform_data/gpio-omap.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -251,9 +252,6 @@ static void zoom2_set_hs_extmute(int mute) } static struct twl4030_gpio_platform_data zoom_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .setup = zoom_twl_gpio_setup, }; @@ -281,7 +279,7 @@ static int __init omap_i2c_init(void) codec_data->hs_extmute = 1; codec_data->set_hs_extmute = zoom2_set_hs_extmute; } - omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata); + omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, NULL, 0); return 0; diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index 4e7e56142e6..4994438e1f4 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -22,7 +22,6 @@ #include <asm/mach/arch.h> #include "common.h" -#include <plat/board.h> #include <plat/usb.h> #include <mach/board-zoom.h> diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 3d9d746b221..cabcfdba524 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -33,11 +33,11 @@ #include <linux/cpufreq.h> #include <linux/slab.h> -#include <plat/cpu.h> #include <plat/clock.h> #include <plat/sram.h> #include <plat/sdrc.h> +#include "soc.h" #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index d6e34dd9e7e..298887b5bf6 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -92,15 +92,13 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, validrate); - pr_debug("clock: SDRC CS0 timing params used:" - " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", + pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); if (sdrc_cs1) - pr_debug("clock: SDRC CS1 timing params used: " - " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", - sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, - sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); + pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", + sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, + sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); if (sdrc_cs1) omap3_configure_core_dpll( diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 04d551b1f7f..19a980956d4 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ - WARN(1, "clock: Could not find parent clock %s in clksel array " - "of clock %s\n", src_clk->name, clk->name); + WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", + clk->name, src_clk->name); return NULL; } @@ -126,8 +126,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, if (max_div == 0) { /* This indicates an error in the clksel data */ - WARN(1, "clock: Could not find divisor for clock %s parent %s" - "\n", clk->name, src_clk->parent->name); + WARN(1, "clock: %s: could not find divisor for parent %s\n", + clk->name, src_clk->parent->name); return 0; } @@ -191,8 +191,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ - WARN(1, "clock: Could not find fieldval %d for clock %s parent " - "%s\n", field_val, clk->name, clk->parent->name); + WARN(1, "clock: %s: could not find fieldval %d parent %s\n", + clk->name, field_val, clk->parent->name); return 0; } @@ -230,8 +230,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) } if (!clkr->div) { - pr_err("clock: Could not find divisor %d for clock %s parent " - "%s\n", div, clk->name, clk->parent->name); + pr_err("clock: %s: could not find divisor %d parent %s\n", + clk->name, div, clk->parent->name); return ~0; } @@ -300,8 +300,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, /* Sanity check */ if (clkr->div <= last_div) - pr_err("clock: clksel_rate table not sorted " - "for clock %s", clk->name); + pr_err("clock: %s: clksel_rate table not sorted", + clk->name); last_div = clkr->div; @@ -312,9 +312,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, } if (!clkr->div) { - pr_err("clock: Could not find divisor for target " - "rate %ld for clock %s parent %s\n", target_rate, - clk->name, clk->parent->name); + pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n", + clk->name, target_rate, clk->parent->name); return ~0; } @@ -359,8 +358,7 @@ void omap2_init_clksel_parent(struct clk *clk) if (clkr->val == r) { if (clk->parent != clks->parent) { - pr_debug("clock: inited %s parent " - "to %s (was %s)\n", + pr_debug("clock: %s: inited parent to %s (was %s)\n", clk->name, clks->parent->name, ((clk->parent) ? clk->parent->name : "NULL")); diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index cd7fd0f9114..83b658bf385 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -22,8 +22,8 @@ #include <asm/div64.h> #include <plat/clock.h> -#include <plat/cpu.h> +#include "soc.h" #include "clock.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" @@ -105,13 +105,13 @@ static int _dpll_test_fint(struct clk *clk, u8 n) } if (fint < fint_min) { - pr_debug("rejecting n=%d due to Fint failure, " - "lowering max_divider\n", n); + pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", + n); dd->max_divider = n; ret = DPLL_FINT_UNDERFLOW; } else if (fint > fint_max) { - pr_debug("rejecting n=%d due to Fint failure, " - "boosting min_divider\n", n); + pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", + n); dd->min_divider = n; ret = DPLL_FINT_INVALID; } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX && @@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk) if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) clk_reparent(clk, dd->clk_bypass); - } else if (cpu_is_omap44xx()) { + } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) @@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk) if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) return dd->clk_bypass->rate; - } else if (cpu_is_omap44xx()) { + } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index ea3f565ba1a..e97f98ffe8b 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -22,14 +22,16 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/bitops.h> -#include <trace/events/power.h> #include <asm/cpu.h> + #include <plat/clock.h> -#include "clockdomain.h" -#include <plat/cpu.h> #include <plat/prcm.h> +#include <trace/events/power.h> + +#include "soc.h" +#include "clockdomain.h" #include "clock.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" @@ -102,8 +104,8 @@ void omap2_init_clk_clkdm(struct clk *clk) clk->name, clk->clkdm_name); clk->clkdm = clkdm; } else { - pr_debug("clock: could not associate clk %s to " - "clkdm %s\n", clk->name, clk->clkdm_name); + pr_debug("clock: could not associate clk %s to clkdm %s\n", + clk->name, clk->clkdm_name); } } @@ -226,8 +228,7 @@ void omap2_dflt_clk_disable(struct clk *clk) * 'Independent' here refers to a clock which is not * controlled by its parent. */ - printk(KERN_ERR "clock: clk_disable called on independent " - "clock %s which has no enable_reg\n", clk->name); + pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name); return; } @@ -270,8 +271,7 @@ const struct clkops clkops_omap2_dflt = { void omap2_clk_disable(struct clk *clk) { if (clk->usecount == 0) { - WARN(1, "clock: %s: omap2_clk_disable() called, but usecount " - "already 0?", clk->name); + WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name); return; } @@ -332,8 +332,8 @@ int omap2_clk_enable(struct clk *clk) if (clkdm_control && clk->clkdm) { ret = clkdm_clk_enable(clk->clkdm, clk); if (ret) { - WARN(1, "clock: %s: could not enable clockdomain %s: " - "%d\n", clk->name, clk->clkdm->name, ret); + WARN(1, "clock: %s: could not enable clockdomain %s: %d\n", + clk->name, clk->clkdm->name, ret); goto oce_err2; } } @@ -501,10 +501,8 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, hfclkin_rate = clk_get_rate(hfclkin_ck); - pr_info("Switched to new clocking rate (Crystal/Core/MPU): " - "%ld.%01ld/%ld/%ld MHz\n", - (hfclkin_rate / 1000000), - ((hfclkin_rate / 100000) % 10), + pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", + (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), (clk_get_rate(core_ck) / 1000000), (clk_get_rate(mpu_ck) / 1000000)); } diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 002745181ad..12c178dbc9f 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -18,9 +18,9 @@ #include <linux/clk.h> #include <linux/list.h> -#include <plat/hardware.h> #include <plat/clkdev_omap.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock2xxx.h" diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index dfda9a3f2cb..a8e32617746 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c @@ -21,9 +21,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clock.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock2xxx.h" diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index cacabb070e2..7ea91398217 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -17,9 +17,9 @@ #include <linux/clk.h> #include <linux/list.h> -#include <plat/hardware.h> #include <plat/clkdev_omap.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock2xxx.h" @@ -1856,6 +1856,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), CLK(NULL, "osc_ck", &osc_ck, CK_243X), + CLK("twl", "fck", &osc_ck, CK_243X), CLK(NULL, "sys_ck", &sys_ck, CK_243X), CLK(NULL, "alt_ck", &alt_ck, CK_243X), CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index 12500097378..e92be1fc1a0 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c @@ -22,9 +22,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/cpu.h> #include <plat/clock.h> +#include "soc.h" #include "clock.h" #include "clock2xxx.h" #include "cm.h" diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c index ae27de8899a..2026311a4ff 100644 --- a/arch/arm/mach-omap2/clock33xx_data.c +++ b/arch/arm/mach-omap2/clock33xx_data.c @@ -18,8 +18,8 @@ #include <linux/list.h> #include <linux/clk.h> #include <plat/clkdev_omap.h> -#include <plat/am33xx.h> +#include "am33xx.h" #include "iomap.h" #include "control.h" #include "clock.h" @@ -1027,7 +1027,9 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), + CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), + CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX), diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 794d82702c8..15cdc647173 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -21,9 +21,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clock.h> +#include "soc.h" #include "clock.h" #include "clock3xxx.h" #include "prm2xxx_3xxx.h" @@ -49,8 +49,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) * on DPLL4. */ if (omap_rev() == OMAP3430_REV_ES1_0) { - pr_err("clock: DPLL4 cannot change rate due to " - "silicon 'Limitation 2.5' on 3430ES1.\n"); + pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); return -EINVAL; } diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 83bed9ad301..700317a1bd1 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -21,9 +21,9 @@ #include <linux/list.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clkdev_omap.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock3xxx.h" @@ -3226,6 +3226,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX), CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), + CLK("twl", "fck", &osc_sys_ck, CK_3XXX), CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index d7f55e43b76..500682c051c 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -28,9 +28,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clkdev_omap.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock44xx.h" diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 8664f5a8bfb..a1555627ad9 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -174,9 +174,8 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm) if (IS_ERR(autodep->clkdm.ptr)) continue; - pr_debug("clockdomain: adding %s sleepdep/wkdep for " - "clkdm %s\n", autodep->clkdm.ptr->name, - clkdm->name); + pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n", + clkdm->name, autodep->clkdm.ptr->name); clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr); clkdm_add_wkdep(clkdm, autodep->clkdm.ptr); @@ -205,9 +204,8 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm) if (IS_ERR(autodep->clkdm.ptr)) continue; - pr_debug("clockdomain: removing %s sleepdep/wkdep for " - "clkdm %s\n", autodep->clkdm.ptr->name, - clkdm->name); + pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n", + clkdm->name, autodep->clkdm.ptr->name); clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr); clkdm_del_wkdep(clkdm, autodep->clkdm.ptr); @@ -469,14 +467,14 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear wake up of " - "%s when %s wakes up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", + clkdm1->name, clkdm2->name); return ret; } if (atomic_inc_return(&cd->wkdep_usecount) == 1) { - pr_debug("clockdomain: hardware will wake up %s when %s wakes " - "up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n", + clkdm1->name, clkdm2->name); ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2); } @@ -510,14 +508,14 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear wake up of " - "%s when %s wakes up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", + clkdm1->name, clkdm2->name); return ret; } if (atomic_dec_return(&cd->wkdep_usecount) == 0) { - pr_debug("clockdomain: hardware will no longer wake up %s " - "after %s wakes up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n", + clkdm1->name, clkdm2->name); ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2); } @@ -555,8 +553,8 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear wake up of " - "%s when %s wakes up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", + clkdm1->name, clkdm2->name); return ret; } @@ -613,15 +611,14 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear sleep " - "dependency affecting %s from %s\n", clkdm1->name, - clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", + clkdm1->name, clkdm2->name); return ret; } if (atomic_inc_return(&cd->sleepdep_usecount) == 1) { - pr_debug("clockdomain: will prevent %s from sleeping if %s " - "is active\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n", + clkdm1->name, clkdm2->name); ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2); } @@ -657,16 +654,14 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear sleep " - "dependency affecting %s from %s\n", clkdm1->name, - clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", + clkdm1->name, clkdm2->name); return ret; } if (atomic_dec_return(&cd->sleepdep_usecount) == 0) { - pr_debug("clockdomain: will no longer prevent %s from " - "sleeping if %s is active\n", clkdm1->name, - clkdm2->name); + pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n", + clkdm1->name, clkdm2->name); ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2); } @@ -706,9 +701,8 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear sleep " - "dependency affecting %s from %s\n", clkdm1->name, - clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", + clkdm1->name, clkdm2->name); return ret; } @@ -755,8 +749,8 @@ int clkdm_sleep(struct clockdomain *clkdm) return -EINVAL; if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { - pr_debug("clockdomain: %s does not support forcing " - "sleep via software\n", clkdm->name); + pr_debug("clockdomain: %s does not support forcing sleep via software\n", + clkdm->name); return -EINVAL; } @@ -790,8 +784,8 @@ int clkdm_wakeup(struct clockdomain *clkdm) return -EINVAL; if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) { - pr_debug("clockdomain: %s does not support forcing " - "wakeup via software\n", clkdm->name); + pr_debug("clockdomain: %s does not support forcing wakeup via software\n", + clkdm->name); return -EINVAL; } @@ -826,8 +820,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm) return; if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) { - pr_debug("clock: automatic idle transitions cannot be enabled " - "on clockdomain %s\n", clkdm->name); + pr_debug("clock: %s: automatic idle transitions cannot be enabled\n", + clkdm->name); return; } @@ -861,8 +855,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm) return; if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) { - pr_debug("clockdomain: automatic idle transitions cannot be " - "disabled on %s\n", clkdm->name); + pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n", + clkdm->name); return; } @@ -927,7 +921,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) pwrdm_state_switch(clkdm->pwrdm.ptr); spin_unlock_irqrestore(&clkdm->lock, flags); - pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name); + pr_debug("clockdomain: %s: enabled\n", clkdm->name); return 0; } @@ -952,7 +946,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) pwrdm_state_switch(clkdm->pwrdm.ptr); spin_unlock_irqrestore(&clkdm->lock, flags); - pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name); + pr_debug("clockdomain: %s: disabled\n", clkdm->name); return 0; } diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 389f9f8b570..a911e76b4ec 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -18,8 +18,7 @@ #include <linux/err.h> #include <linux/io.h> -#include <plat/hardware.h> - +#include "soc.h" #include "iomap.h" #include "common.h" #include "cm.h" diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c index c1875862679..48daac2581b 100644 --- a/arch/arm/mach-omap2/common-board-devices.c +++ b/arch/arm/mach-omap2/common-board-devices.c @@ -24,9 +24,10 @@ #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> -#include <plat/mcspi.h> -#include <plat/nand.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/mtd-nand-omap2.h> +#include "common.h" #include "common-board-devices.h" #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ @@ -119,8 +120,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts, } if (nandcs > GPMC_CS_NUM) { - printk(KERN_INFO "NAND: Unable to find configuration " - "in GPMC\n "); + pr_info("NAND: Unable to find configuration in GPMC\n"); return; } diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 069f9725b1c..17950c6e130 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -17,11 +17,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> -#include <plat/board.h> -#include <plat/mux.h> #include <plat/clock.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 1f65b1871c2..7045e4d61ac 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -26,11 +26,18 @@ #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H #ifndef __ASSEMBLER__ +#include <linux/irq.h> #include <linux/delay.h> #include <linux/i2c/twl.h> -#include <plat/common.h> + #include <asm/proc-fns.h> +#include <plat/cpu.h> +#include <plat/serial.h> +#include <plat/common.h> + +#define OMAP_INTC_START NR_IRQS + #ifdef CONFIG_SOC_OMAP2420 extern void omap242x_map_common_io(void); #else @@ -278,6 +285,11 @@ extern void omap_secondary_startup(void); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); extern void omap_auxcoreboot_addr(u32 cpu_addr); extern u32 omap_read_auxcoreboot0(void); + +extern void omap4_cpu_die(unsigned int cpu); + +extern struct smp_operations omap4_smp_ops; + extern void omap5_secondary_startup(void); #endif diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 3223b81e753..d1ff8399a22 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -15,9 +15,9 @@ #include <linux/kernel.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/sdrc.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "cm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index b8cdc8531b6..123186ac7d2 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -16,12 +16,12 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H #define __ARCH_ARM_MACH_OMAP2_CONTROL_H -#include <mach/ctrl_module_core_44xx.h> -#include <mach/ctrl_module_wkup_44xx.h> -#include <mach/ctrl_module_pad_core_44xx.h> -#include <mach/ctrl_module_pad_wkup_44xx.h> +#include "ctrl_module_core_44xx.h" +#include "ctrl_module_wkup_44xx.h" +#include "ctrl_module_pad_core_44xx.h" +#include "ctrl_module_pad_wkup_44xx.h" -#include <plat/am33xx.h> +#include "am33xx.h" #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index f2a49a48ef5..bc2756959be 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -28,7 +28,6 @@ #include <linux/cpu_pm.h> #include <plat/prcm.h> -#include <plat/irqs.h> #include "powerdomain.h" #include "clockdomain.h" diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_core_44xx.h index 01970824e0e..01970824e0e 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h +++ b/arch/arm/mach-omap2/ctrl_module_core_44xx.h diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h index c88420de115..c88420de115 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h +++ b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h index 17c9b37042c..17c9b37042c 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h +++ b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h index a0af9baec3f..a0af9baec3f 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h +++ b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h diff --git a/arch/arm/mach-omap2/debug-devices.h b/arch/arm/mach-omap2/debug-devices.h new file mode 100644 index 00000000000..a4edbd2f748 --- /dev/null +++ b/arch/arm/mach-omap2/debug-devices.h @@ -0,0 +1,9 @@ +#ifndef _OMAP_DEBUG_DEVICES_H +#define _OMAP_DEBUG_DEVICES_H + +#include <linux/types.h> + +/* for TI reference platforms sharing the same debug card */ +extern int debug_card_init(u32 addr, unsigned gpio); + +#endif diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index c00c68961bb..d092d2a89ee 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -17,21 +17,20 @@ #include <linux/err.h> #include <linux/slab.h> #include <linux/of.h> +#include <linux/pinctrl/machine.h> #include <linux/platform_data/omap4-keypad.h> -#include <mach/hardware.h> -#include <mach/irqs.h> #include <asm/mach-types.h> #include <asm/mach/map.h> -#include <asm/pmu.h> #include "iomap.h" -#include <plat/board.h> #include <plat/dma.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> -#include <plat/omap4-keypad.h> +#include "omap4-keypad.h" +#include "soc.h" +#include "common.h" #include "mux.h" #include "control.h" #include "devices.h" @@ -112,7 +111,7 @@ static struct resource omap2cam_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_24XX_CAM_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, } }; @@ -201,7 +200,7 @@ static struct resource omap3isp_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_34XX_CAM_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, } }; @@ -385,7 +384,7 @@ static inline void omap_init_hdmi_audio(void) {} #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused) { @@ -435,20 +434,18 @@ static inline void omap_init_mcspi(void) {} #endif static struct resource omap2_pmu_resource = { - .start = 3, - .end = 3, + .start = 3 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }; static struct resource omap3_pmu_resource = { - .start = INT_34XX_BENCH_MPU_EMUL, - .end = INT_34XX_BENCH_MPU_EMUL, + .start = 3 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }; static struct platform_device omap_pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = 1, }; @@ -475,7 +472,7 @@ static struct resource omap2_sham_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_24XX_SHA1MD5, + .start = 51 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, } }; @@ -493,7 +490,7 @@ static struct resource omap3_sham_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_34XX_SHA1MD52_IRQ, + .start = 49 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }, { @@ -631,6 +628,10 @@ static inline void omap_init_vout(void) {} static int __init omap2_init_devices(void) { + /* Enable dummy states for those platforms without pinctrl support */ + if (!of_have_populated_dt()) + pinctrl_provide_dummies(); + /* * please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index b9c8d2f6a81..27d79deb4ba 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -28,9 +28,9 @@ #include <linux/bitops.h> #include <linux/clkdev.h> -#include <plat/cpu.h> #include <plat/clock.h> +#include "soc.h" #include "clock.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" @@ -311,7 +311,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) * Set jitter correction. No jitter correction for OMAP4 and 3630 * since freqsel field is no longer present */ - if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { + if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { v = __raw_readl(dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -471,7 +471,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; /* No freqsel on OMAP4 and OMAP3630 */ - if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { + if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); if (!freqsel) @@ -623,8 +623,11 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) while (pclk && !pclk->dpll_data) pclk = pclk->parent; - /* clk does not have a DPLL as a parent? */ - WARN_ON(!pclk); + /* clk does not have a DPLL as a parent? error in the clock data */ + if (!pclk) { + WARN_ON(1); + return 0; + } dd = pclk->dpll_data; diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 9c6a296b3dc..09d0ccccb86 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -15,9 +15,9 @@ #include <linux/io.h> #include <linux/bitops.h> -#include <plat/cpu.h> #include <plat/clock.h> +#include "soc.h" #include "clock.h" #include "clock44xx.h" #include "cm-regbits-44xx.h" diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index a636ebc16b3..98388109f22 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -30,7 +30,7 @@ #include <plat/omap-pm.h> #endif -#include <plat/dsp.h> +#include <linux/platform_data/dsp-omap.h> static struct platform_device *omap_dsp_pdev; diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c index e28e761b7ab..b3566f68a55 100644 --- a/arch/arm/mach-omap2/emu.c +++ b/arch/arm/mach-omap2/emu.c @@ -21,8 +21,7 @@ #include <linux/clk.h> #include <linux/err.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 9ad7d489b0d..d1058f16fb4 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c @@ -21,6 +21,7 @@ #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/of.h> +#include <linux/platform_data/gpio-omap.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> @@ -60,6 +61,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); if (!pdata->regs) { pr_err("gpio%d: Memory allocation failed\n", id); + kfree(pdata); return -ENOMEM; } @@ -121,6 +123,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) break; default: WARN(1, "Invalid gpio bank_type\n"); + kfree(pdata->regs); kfree(pdata); return -EINVAL; } diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 386dec8d235..4acf497faeb 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -13,23 +13,31 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/mtd/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <asm/mach/flash.h> -#include <plat/cpu.h> -#include <plat/nand.h> -#include <plat/board.h> #include <plat/gpmc.h> -static struct resource gpmc_nand_resource = { - .flags = IORESOURCE_MEM, +#include "soc.h" + +static struct resource gpmc_nand_resource[] = { + { + .flags = IORESOURCE_MEM, + }, + { + .flags = IORESOURCE_IRQ, + }, + { + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device gpmc_nand_device = { .name = "omap2-nand", .id = 0, - .num_resources = 1, - .resource = &gpmc_nand_resource, + .num_resources = ARRAY_SIZE(gpmc_nand_resource), + .resource = gpmc_nand_resource, }; static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data) @@ -75,6 +83,7 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0); err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); if (err) return err; @@ -90,12 +99,19 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) gpmc_nand_device.dev.platform_data = gpmc_nand_data; err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, - &gpmc_nand_data->phys_base); + (unsigned long *)&gpmc_nand_resource[0].start); if (err < 0) { dev_err(dev, "Cannot request GPMC CS\n"); return err; } + gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + + NAND_IO_SIZE - 1; + + gpmc_nand_resource[1].start = + gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); + gpmc_nand_resource[2].start = + gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); /* Set timings in GPMC */ err = omap2_nand_gpmc_retime(gpmc_nand_data); if (err < 0) { @@ -108,6 +124,8 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); } + gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); + err = platform_device_register(&gpmc_nand_device); if (err < 0) { dev_err(dev, "Unable to register NAND device\n"); diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index a0fa9bb2bda..916716e1da3 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -15,19 +15,27 @@ #include <linux/platform_device.h> #include <linux/mtd/onenand_regs.h> #include <linux/io.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include <asm/mach/flash.h> -#include <plat/cpu.h> -#include <plat/onenand.h> -#include <plat/board.h> #include <plat/gpmc.h> +#include "soc.h" + +#define ONENAND_IO_SIZE SZ_128K + static struct omap_onenand_platform_data *gpmc_onenand_data; +static struct resource gpmc_onenand_resource = { + .flags = IORESOURCE_MEM, +}; + static struct platform_device gpmc_onenand_device = { .name = "omap2-onenand", .id = -1, + .num_resources = 1, + .resource = &gpmc_onenand_resource, }; static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) @@ -390,6 +398,8 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) { + int err; + gpmc_onenand_data = _onenand_data; gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; @@ -401,8 +411,19 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) gpmc_onenand_data->flags |= ONENAND_SYNC_READ; } + err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, + (unsigned long *)&gpmc_onenand_resource.start); + if (err < 0) { + pr_err("%s: Cannot request GPMC CS\n", __func__); + return; + } + + gpmc_onenand_resource.end = gpmc_onenand_resource.start + + ONENAND_IO_SIZE - 1; + if (platform_device_register(&gpmc_onenand_device) < 0) { - printk(KERN_ERR "Unable to register OneNAND device\n"); + pr_err("%s: Unable to register OneNAND device\n", __func__); + gpmc_cs_free(gpmc_onenand_data->cs); return; } } diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c index ba10c24f3d8..56547531037 100644 --- a/arch/arm/mach-omap2/gpmc-smc91x.c +++ b/arch/arm/mach-omap2/gpmc-smc91x.c @@ -17,9 +17,10 @@ #include <linux/io.h> #include <linux/smc91x.h> -#include <plat/board.h> #include <plat/gpmc.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" + +#include "soc.h" static struct omap_smc91x_platform_data *gpmc_cfg; diff --git a/arch/arm/mach-omap2/gpmc-smc91x.h b/arch/arm/mach-omap2/gpmc-smc91x.h new file mode 100644 index 00000000000..b64fbee4d56 --- /dev/null +++ b/arch/arm/mach-omap2/gpmc-smc91x.h @@ -0,0 +1,42 @@ +/* + * arch/arm/plat-omap/include/mach/gpmc-smc91x.h + * + * Copyright (C) 2009 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__ + +#define GPMC_TIMINGS_SMC91C96 (1 << 4) +#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */ +#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */ +#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */ + +struct omap_smc91x_platform_data { + int cs; + int gpio_irq; + int gpio_pwrdwn; + int gpio_reset; + int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */ + u32 flags; + int (*retime)(void); +}; + +#if defined(CONFIG_SMC91X) || \ + defined(CONFIG_SMC91X_MODULE) + +extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d); + +#else + +#define board_smc91x_data NULL + +static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d) +{ +} + +#endif +#endif diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c index b6c77be3e8f..249a0b440cd 100644 --- a/arch/arm/mach-omap2/gpmc-smsc911x.c +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c @@ -20,9 +20,8 @@ #include <linux/io.h> #include <linux/smsc911x.h> -#include <plat/board.h> #include <plat/gpmc.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct resource gpmc_smsc911x_resources[] = { [0] = { diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.h b/arch/arm/mach-omap2/gpmc-smsc911x.h new file mode 100644 index 00000000000..ea6c9c88c72 --- /dev/null +++ b/arch/arm/mach-omap2/gpmc-smsc911x.h @@ -0,0 +1,35 @@ +/* + * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h + * + * Copyright (C) 2009 Li-Pro.Net + * Stephan Linz <linz@li-pro.net> + * + * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__ + +struct omap_smsc911x_platform_data { + int id; + int cs; + int gpio_irq; + int gpio_reset; + u32 flags; +}; + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) + +extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d); + +#else + +static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d) +{ +} + +#endif +#endif diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index b2b5759ab0f..72428bd45ef 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -28,8 +28,13 @@ #include <asm/mach-types.h> #include <plat/gpmc.h> +#include <plat/cpu.h> +#include <plat/gpmc.h> #include <plat/sdrc.h> +#include "soc.h" +#include "common.h" + /* GPMC register offsets */ #define GPMC_REVISION 0x00 #define GPMC_SYSCONFIG 0x10 @@ -78,6 +83,15 @@ #define ENABLE_PREFETCH (0x1 << 7) #define DMA_MPU_MODE 2 +/* XXX: Only NAND irq has been considered,currently these are the only ones used + */ +#define GPMC_NR_IRQ 2 + +struct gpmc_client_irq { + unsigned irq; + u32 bitmask; +}; + /* Structure to save gpmc cs context */ struct gpmc_cs_config { u32 config1; @@ -105,6 +119,10 @@ struct omap3_gpmc_regs { struct gpmc_cs_config cs_context[GPMC_CS_NUM]; }; +static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; +static struct irq_chip gpmc_irq_chip; +static unsigned gpmc_irq_start; + static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); @@ -279,7 +297,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) div = gpmc_cs_calc_divider(cs, t->sync_clk); if (div < 0) - return -1; + return div; GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); @@ -682,6 +700,117 @@ int gpmc_prefetch_reset(int cs) } EXPORT_SYMBOL(gpmc_prefetch_reset); +void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) +{ + reg->gpmc_status = gpmc_base + GPMC_STATUS; + reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + + GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; + reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + + GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; + reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + + GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; + reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; + reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; + reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; + reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; + reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; + reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; + reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; + reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; + reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0; +} + +int gpmc_get_client_irq(unsigned irq_config) +{ + int i; + + if (hweight32(irq_config) > 1) + return 0; + + for (i = 0; i < GPMC_NR_IRQ; i++) + if (gpmc_client_irq[i].bitmask & irq_config) + return gpmc_client_irq[i].irq; + + return 0; +} + +static int gpmc_irq_endis(unsigned irq, bool endis) +{ + int i; + u32 regval; + + for (i = 0; i < GPMC_NR_IRQ; i++) + if (irq == gpmc_client_irq[i].irq) { + regval = gpmc_read_reg(GPMC_IRQENABLE); + if (endis) + regval |= gpmc_client_irq[i].bitmask; + else + regval &= ~gpmc_client_irq[i].bitmask; + gpmc_write_reg(GPMC_IRQENABLE, regval); + break; + } + + return 0; +} + +static void gpmc_irq_disable(struct irq_data *p) +{ + gpmc_irq_endis(p->irq, false); +} + +static void gpmc_irq_enable(struct irq_data *p) +{ + gpmc_irq_endis(p->irq, true); +} + +static void gpmc_irq_noop(struct irq_data *data) { } + +static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } + +static int gpmc_setup_irq(int gpmc_irq) +{ + int i; + u32 regval; + + if (!gpmc_irq) + return -EINVAL; + + gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); + if (IS_ERR_VALUE(gpmc_irq_start)) { + pr_err("irq_alloc_descs failed\n"); + return gpmc_irq_start; + } + + gpmc_irq_chip.name = "gpmc"; + gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; + gpmc_irq_chip.irq_enable = gpmc_irq_enable; + gpmc_irq_chip.irq_disable = gpmc_irq_disable; + gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; + gpmc_irq_chip.irq_ack = gpmc_irq_noop; + gpmc_irq_chip.irq_mask = gpmc_irq_noop; + gpmc_irq_chip.irq_unmask = gpmc_irq_noop; + + gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; + gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; + + for (i = 0; i < GPMC_NR_IRQ; i++) { + gpmc_client_irq[i].irq = gpmc_irq_start + i; + irq_set_chip_and_handler(gpmc_client_irq[i].irq, + &gpmc_irq_chip, handle_simple_irq); + set_irq_flags(gpmc_client_irq[i].irq, + IRQF_VALID | IRQF_NOAUTOEN); + } + + /* Disable interrupts */ + gpmc_write_reg(GPMC_IRQENABLE, 0); + + /* clear interrupts */ + regval = gpmc_read_reg(GPMC_IRQSTATUS); + gpmc_write_reg(GPMC_IRQSTATUS, regval); + + return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); +} + static void __init gpmc_mem_init(void) { int cs; @@ -711,8 +840,8 @@ static void __init gpmc_mem_init(void) static int __init gpmc_init(void) { - u32 l, irq; - int cs, ret = -EINVAL; + u32 l; + int ret = -EINVAL; int gpmc_irq; char *ck = NULL; @@ -722,16 +851,16 @@ static int __init gpmc_init(void) l = OMAP2420_GPMC_BASE; else l = OMAP34XX_GPMC_BASE; - gpmc_irq = INT_34XX_GPMC_IRQ; + gpmc_irq = 20 + OMAP_INTC_START; } else if (cpu_is_omap34xx()) { ck = "gpmc_fck"; l = OMAP34XX_GPMC_BASE; - gpmc_irq = INT_34XX_GPMC_IRQ; + gpmc_irq = 20 + OMAP_INTC_START; } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { /* Base address and irq number are same for OMAP4/5 */ ck = "gpmc_ck"; l = OMAP44XX_GPMC_BASE; - gpmc_irq = OMAP44XX_IRQ_GPMC; + gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START; } if (WARN_ON(!ck)) @@ -761,16 +890,7 @@ static int __init gpmc_init(void) gpmc_write_reg(GPMC_SYSCONFIG, l); gpmc_mem_init(); - /* initalize the irq_chained */ - irq = OMAP_GPMC_IRQ_BASE; - for (cs = 0; cs < GPMC_CS_NUM; cs++) { - irq_set_chip_and_handler(irq, &dummy_irq_chip, - handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); - irq++; - } - - ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL); + ret = gpmc_setup_irq(gpmc_irq); if (ret) pr_err("gpmc: irq-%d could not claim: err %d\n", gpmc_irq, ret); @@ -780,12 +900,19 @@ postcore_initcall(gpmc_init); static irqreturn_t gpmc_handle_irq(int irq, void *dev) { - u8 cs; + int i; + u32 regval; + + regval = gpmc_read_reg(GPMC_IRQSTATUS); + + if (!regval) + return IRQ_NONE; + + for (i = 0; i < GPMC_NR_IRQ; i++) + if (regval & gpmc_client_irq[i].bitmask) + generic_handle_irq(gpmc_client_irq[i].irq); - /* check cs to invoke the irq */ - cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; - if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) - generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); + gpmc_write_reg(GPMC_IRQSTATUS, regval); return IRQ_HANDLED; } diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c index cdd6dda0382..e003f2bba30 100644 --- a/arch/arm/mach-omap2/hdq1w.c +++ b/arch/arm/mach-omap2/hdq1w.c @@ -29,7 +29,7 @@ #include <plat/omap_hwmod.h> #include <plat/omap_device.h> -#include <plat/hdq1w.h> +#include "hdq1w.h" #include "common.h" diff --git a/arch/arm/mach-omap2/hdq1w.h b/arch/arm/mach-omap2/hdq1w.h new file mode 100644 index 00000000000..0c1efc846d8 --- /dev/null +++ b/arch/arm/mach-omap2/hdq1w.h @@ -0,0 +1,36 @@ +/* + * Shared macros and function prototypes for the HDQ1W/1-wire IP block + * + * Copyright (C) 2012 Texas Instruments, Inc. + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H +#define ARCH_ARM_MACH_OMAP2_HDQ1W_H + +#include <plat/omap_hwmod.h> + +/* + * XXX A future cleanup patch should modify + * drivers/w1/masters/omap_hdq.c to use these macros + */ +#define HDQ_CTRL_STATUS_OFFSET 0x0c +#define HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT 5 + + +extern int omap_hdq1w_reset(struct omap_hwmod *oh); + +#endif diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index a9675d8d182..03ebf47cfa9 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -15,9 +15,10 @@ #include <linux/delay.h> #include <linux/gpio.h> #include <mach/hardware.h> +#include <linux/platform_data/gpio-omap.h> + #include <plat/mmc.h> #include <plat/omap-pm.h> -#include <plat/mux.h> #include <plat/omap_device.h> #include "mux.h" diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index a12e224eb97..fc57e67b321 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c @@ -19,7 +19,6 @@ * */ -#include <plat/cpu.h> #include <plat/i2c.h> #include "common.h" #include <plat/omap_hwmod.h> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 40373db649a..cf2362ccb23 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -22,10 +22,10 @@ #include <asm/cputype.h> #include "common.h" -#include <plat/cpu.h> -#include <mach/id.h> +#include "id.h" +#include "soc.h" #include "control.h" static unsigned int omap_revision; @@ -161,9 +161,8 @@ void __init omap2xxx_check_revision(void) } if (j == ARRAY_SIZE(omap_ids)) { - printk(KERN_ERR "Unknown OMAP device type. " - "Handling it as OMAP%04x\n", - omap_ids[i].type >> 16); + pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", + omap_ids[i].type >> 16); j = i; } diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/id.h index 02ed3aa56f1..02ed3aa56f1 100644 --- a/arch/arm/mach-omap2/include/mach/id.h +++ b/arch/arm/mach-omap2/id.h diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h index be4d290d57e..5621cc59c9f 100644 --- a/arch/arm/mach-omap2/include/mach/gpio.h +++ b/arch/arm/mach-omap2/include/mach/gpio.h @@ -1,5 +1,3 @@ /* * arch/arm/mach-omap2/include/mach/gpio.h */ - -#include <plat/gpio.h> diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h index 78edf9d33f7..54492dbf697 100644 --- a/arch/arm/mach-omap2/include/mach/hardware.h +++ b/arch/arm/mach-omap2/include/mach/hardware.h @@ -1,5 +1,3 @@ /* * arch/arm/mach-omap2/include/mach/hardware.h */ - -#include <plat/hardware.h> diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h index 44dab772569..ba5282cafa4 100644 --- a/arch/arm/mach-omap2/include/mach/irqs.h +++ b/arch/arm/mach-omap2/include/mach/irqs.h @@ -1,5 +1,3 @@ /* * arch/arm/mach-omap2/include/mach/irqs.h */ - -#include <plat/irqs.h> diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h deleted file mode 100644 index 323675f21b6..00000000000 --- a/arch/arm/mach-omap2/include/mach/smp.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * arch/arm/mach-omap2/include/mach/smp.h - */ - -#include <plat/smp.h> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4d2d981ff5c..4234d28dc17 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -33,6 +33,7 @@ #include <plat/multi.h> #include <plat/dma.h> +#include "soc.h" #include "iomap.h" #include "voltage.h" #include "powerdomain.h" @@ -523,6 +524,8 @@ void __init am33xx_init_early(void) am33xx_voltagedomains_init(); am33xx_powerdomains_init(); am33xx_clockdomains_init(); + am33xx_hwmod_init(); + omap_hwmod_init_postsetup(); am33xx_clk_init(); } #endif diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bcd83db41bb..3926f370448 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -23,8 +23,7 @@ #include <linux/of_address.h> #include <linux/of_irq.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" #include "common.h" @@ -49,6 +48,8 @@ #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ +#define INTCPS_NR_MIR_REGS 3 +#define INTCPS_NR_IRQS 96 /* * OMAP2 has a number of different interrupt controllers, each interrupt @@ -107,9 +108,8 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) unsigned long tmp; tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff; - printk(KERN_INFO "IRQ: Found an INTC at 0x%p " - "(revision %ld.%ld) with %d interrupts\n", - bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); + pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", + bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG); tmp |= 1 << 1; /* soft reset */ diff --git a/arch/arm/mach-omap2/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h new file mode 100644 index 00000000000..b8b5641379b --- /dev/null +++ b/arch/arm/mach-omap2/l3_2xxx.h @@ -0,0 +1,20 @@ +/* + * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H + +/* L3 CONNIDs */ +/* Display Sub system (DSS) */ +#define OMAP2_L3_CORE_FW_CONNID_DSS 8 + +#endif diff --git a/arch/arm/mach-omap2/l3_3xxx.h b/arch/arm/mach-omap2/l3_3xxx.h new file mode 100644 index 00000000000..cde1938c5f8 --- /dev/null +++ b/arch/arm/mach-omap2/l3_3xxx.h @@ -0,0 +1,20 @@ +/* + * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H + +/* L3 Initiator IDs */ +/* Display Sub system (DSS) */ +#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29 + +#endif diff --git a/arch/arm/mach-omap2/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h new file mode 100644 index 00000000000..3f39cf8a35c --- /dev/null +++ b/arch/arm/mach-omap2/l4_2xxx.h @@ -0,0 +1,24 @@ +/* + * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H + +/* L4 CORE */ +/* Display Sub system (DSS) */ +#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28 +#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29 +#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30 +#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31 +#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32 + +#endif diff --git a/arch/arm/mach-omap2/l4_3xxx.h b/arch/arm/mach-omap2/l4_3xxx.h new file mode 100644 index 00000000000..881a858b1ff --- /dev/null +++ b/arch/arm/mach-omap2/l4_3xxx.h @@ -0,0 +1,34 @@ +/* + * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H + +/* L4 CORE */ +#define OMAP3_L4_CORE_FW_I2C1_REGION 21 +#define OMAP3_L4_CORE_FW_I2C1_TA_REGION 22 +#define OMAP3_L4_CORE_FW_I2C2_REGION 23 +#define OMAP3_L4_CORE_FW_I2C2_TA_REGION 24 +#define OMAP3_L4_CORE_FW_I2C3_REGION 73 +#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 + +/* Display Sub system (DSS) */ +#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2 + +#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104 +#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3 +#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4 +#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4 +#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5 +#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6 +#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7 +#endif diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 6875be837d9..0d974565f8c 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -16,8 +16,10 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/pm_runtime.h> + #include <plat/mailbox.h> -#include <mach/irqs.h> + +#include "soc.h" #define MAILBOX_REVISION 0x000 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 577cb77db26..7d47407d6d4 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -17,11 +17,9 @@ #include <linux/io.h> #include <linux/platform_device.h> #include <linux/slab.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> -#include <mach/irqs.h> #include <plat/dma.h> -#include <plat/cpu.h> -#include <plat/mcbsp.h> #include <plat/omap_device.h> #include <linux/pm_runtime.h> diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c index fb5bc6cf377..9e57b4aadb0 100644 --- a/arch/arm/mach-omap2/msdi.c +++ b/arch/arm/mach-omap2/msdi.c @@ -23,6 +23,7 @@ #include <linux/kernel.h> #include <linux/err.h> +#include <linux/platform_data/gpio-omap.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c index 414083b427d..e712d1725a8 100644 --- a/arch/arm/mach-omap2/omap-hotplug.c +++ b/arch/arm/mach-omap2/omap-hotplug.c @@ -20,22 +20,17 @@ #include <linux/io.h> #include <asm/cacheflush.h> -#include <mach/omap-wakeupgen.h> +#include "omap-wakeupgen.h" #include "common.h" #include "powerdomain.h" -int platform_cpu_kill(unsigned int cpu) -{ - return 1; -} - /* * platform-specific code to shutdown a CPU * Called with IRQs disabled */ -void __ref platform_cpu_die(unsigned int cpu) +void __ref omap4_cpu_die(unsigned int cpu) { unsigned int boot_cpu = 0; void __iomem *base = omap_get_wakeupgen_base(); @@ -75,12 +70,3 @@ void __ref platform_cpu_die(unsigned int cpu) pr_debug("CPU%u: spurious wakeup call\n", cpu); } } - -int platform_cpu_disable(unsigned int cpu) -{ - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index 1be8bcb52e9..df298d46707 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -14,7 +14,9 @@ #include <linux/platform_device.h> #include <plat/iommu.h> -#include <plat/irqs.h> + +#include "soc.h" +#include "common.h" struct iommu_device { resource_size_t base; @@ -29,7 +31,7 @@ static int num_iommu_devices; static struct iommu_device omap3_devices[] = { { .base = 0x480bd400, - .irq = 24, + .irq = 24 + OMAP_INTC_START, .pdata = { .name = "isp", .nr_tlb_entries = 8, @@ -41,7 +43,7 @@ static struct iommu_device omap3_devices[] = { #if defined(CONFIG_OMAP_IOMMU_IVA2) { .base = 0x5d000000, - .irq = 28, + .irq = 28 + OMAP_INTC_START, .pdata = { .name = "iva2", .nr_tlb_entries = 32, @@ -64,7 +66,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; static struct iommu_device omap4_devices[] = { { .base = OMAP4_MMU1_BASE, - .irq = OMAP44XX_IRQ_DUCATI_MMU, + .irq = 100 + OMAP44XX_IRQ_GIC_START, .pdata = { .name = "ducati", .nr_tlb_entries = 32, @@ -75,7 +77,7 @@ static struct iommu_device omap4_devices[] = { }, { .base = OMAP4_MMU2_BASE, - .irq = OMAP44XX_IRQ_TESLA_MMU, + .irq = 28 + OMAP44XX_IRQ_GIC_START, .pdata = { .name = "tesla", .nr_tlb_entries = 32, diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 637a1bdf2ac..ff4e6a0e9c7 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -50,9 +50,8 @@ #include <asm/suspend.h> #include <asm/hardware/cache-l2x0.h> -#include <plat/omap44xx.h> - #include "common.h" +#include "omap44xx.h" #include "omap4-sar-layout.h" #include "pm.h" #include "prcm_mpu44xx.h" diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index d9ae4a53d81..a004cb9acf5 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -19,7 +19,7 @@ #include <asm/memblock.h> #include <plat/omap-secure.h> -#include <mach/omap-secure.h> +#include "omap-secure.h" static phys_addr_t omap_secure_memblock_base; diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index c90a43589ab..c90a43589ab 100644 --- a/arch/arm/mach-omap2/include/mach/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 9a35adf9123..4d05fa8a4e4 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -24,11 +24,11 @@ #include <asm/hardware/gic.h> #include <asm/smp_scu.h> -#include <mach/hardware.h> -#include <mach/omap-secure.h> -#include <mach/omap-wakeupgen.h> +#include "omap-secure.h" +#include "omap-wakeupgen.h" #include <asm/cputype.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "clockdomain.h" @@ -49,7 +49,7 @@ void __iomem *omap4_get_scu_base(void) return scu_base; } -void __cpuinit platform_secondary_init(unsigned int cpu) +static void __cpuinit omap4_secondary_init(unsigned int cpu) { /* * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. @@ -77,7 +77,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) { static struct clockdomain *cpu1_clkdm; static bool booted; @@ -165,7 +165,7 @@ static void __init wakeup_secondary(void) * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ -void __init smp_init_cpus(void) +static void __init omap4_smp_init_cpus(void) { unsigned int i = 0, ncores = 1, cpu_id; @@ -196,7 +196,7 @@ void __init smp_init_cpus(void) set_smp_cross_call(gic_raise_softirq); } -void __init platform_smp_prepare_cpus(unsigned int max_cpus) +static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) { /* @@ -207,3 +207,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) scu_enable(scu_base); wakeup_secondary(); } + +struct smp_operations omap4_smp_ops __initdata = { + .smp_init_cpus = omap4_smp_init_cpus, + .smp_prepare_cpus = omap4_smp_prepare_cpus, + .smp_secondary_init = omap4_secondary_init, + .smp_boot_secondary = omap4_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = omap4_cpu_die, +#endif +}; diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 330d4c6e746..5d3b4f4f81a 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -27,9 +27,10 @@ #include <asm/hardware/gic.h> -#include <mach/omap-wakeupgen.h> -#include <mach/omap-secure.h> +#include "omap-wakeupgen.h" +#include "omap-secure.h" +#include "soc.h" #include "omap4-sar-layout.h" #include "common.h" @@ -229,13 +230,7 @@ static inline void omap4_irq_save_context(void) /* Save AuxBoot* registers */ val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); - __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); - - /* Save SyncReq generation logic */ - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); - __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); /* Save SyncReq generation logic */ diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h index b0fd16f5c39..b0fd16f5c39 100644 --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +++ b/arch/arm/mach-omap2/omap-wakeupgen.h diff --git a/arch/arm/mach-omap2/omap24xx.h b/arch/arm/mach-omap2/omap24xx.h new file mode 100644 index 00000000000..641a2c8d2ee --- /dev/null +++ b/arch/arm/mach-omap2/omap24xx.h @@ -0,0 +1,87 @@ +/* + * This file contains the processor specific definitions + * of the TI OMAP24XX. + * + * Copyright (C) 2007 Texas Instruments. + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_OMAP2_H +#define __ASM_ARCH_OMAP2_H + +/* + * Please place only base defines here and put the rest in device + * specific headers. Note also that some of these defines are needed + * for omap1 to compile without adding ifdefs. + */ + +#define L4_24XX_BASE 0x48000000 +#define L4_WK_243X_BASE 0x49000000 +#define L3_24XX_BASE 0x68000000 + +/* interrupt controller */ +#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) +#define OMAP24XX_IVA_INTC_BASE 0x40000000 + +#define OMAP242X_CTRL_BASE L4_24XX_BASE +#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) +#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) +#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) +#define OMAP2420_PRM_BASE OMAP2420_CM_BASE +#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) +#define OMAP2420_SMS_BASE 0x68008000 +#define OMAP2420_GPMC_BASE 0x6800a000 + +#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) +#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) +#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000) +#define OMAP2430_PRM_BASE OMAP2430_CM_BASE + +#define OMAP243X_SMS_BASE 0x6C000000 +#define OMAP243X_SDRC_BASE 0x6D000000 +#define OMAP243X_GPMC_BASE 0x6E000000 +#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000) +#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE +#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000) + +/* DSP SS */ +#define OMAP2420_DSP_BASE 0x58000000 +#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0) +#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000) +#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000) + +#define OMAP243X_DSP_BASE 0x5C000000 +#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0) +#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000) + +/* Mailbox */ +#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000) + +/* Camera */ +#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000) + +/* Security */ +#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000) +#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000) +#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000) +#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000) +#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) +#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) + +#endif /* __ASM_ARCH_OMAP2_H */ + diff --git a/arch/arm/mach-omap2/omap34xx.h b/arch/arm/mach-omap2/omap34xx.h new file mode 100644 index 00000000000..c0d1b4b1653 --- /dev/null +++ b/arch/arm/mach-omap2/omap34xx.h @@ -0,0 +1,99 @@ +/* + * This file contains the processor specific definitions of the TI OMAP34XX. + * + * Copyright (C) 2007 Texas Instruments. + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP3_H +#define __ASM_ARCH_OMAP3_H + +/* + * Please place only base defines here and put the rest in device + * specific headers. + */ + +#define L4_34XX_BASE 0x48000000 +#define L4_WK_34XX_BASE 0x48300000 +#define L4_PER_34XX_BASE 0x49000000 +#define L4_EMU_34XX_BASE 0x54000000 +#define L3_34XX_BASE 0x68000000 + +#define L4_WK_AM33XX_BASE 0x44C00000 + +#define OMAP3430_32KSYNCT_BASE 0x48320000 +#define OMAP3430_CM_BASE 0x48004800 +#define OMAP3430_PRM_BASE 0x48306800 +#define OMAP343X_SMS_BASE 0x6C000000 +#define OMAP343X_SDRC_BASE 0x6D000000 +#define OMAP34XX_GPMC_BASE 0x6E000000 +#define OMAP343X_SCM_BASE 0x48002000 +#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE + +#define OMAP34XX_IC_BASE 0x48200000 + +#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) +#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100) +#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400) +#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600) +#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00) +#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00) +#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00) +#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000) +#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200) +#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) +#define OMAP3430_ISP_CSI2A_REGS1_BASE (OMAP3430_ISP_BASE + 0x1800) +#define OMAP3430_ISP_CSIPHY2_BASE (OMAP3430_ISP_BASE + 0x1970) +#define OMAP3630_ISP_CSI2A_REGS2_BASE (OMAP3430_ISP_BASE + 0x19C0) +#define OMAP3630_ISP_CSI2C_REGS1_BASE (OMAP3430_ISP_BASE + 0x1C00) +#define OMAP3630_ISP_CSIPHY1_BASE (OMAP3430_ISP_BASE + 0x1D70) +#define OMAP3630_ISP_CSI2C_REGS2_BASE (OMAP3430_ISP_BASE + 0x1DC0) + +#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F) +#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077) +#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF) +#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7) +#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047) +#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F) +#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F) +#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB) +#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB) +#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F) +#define OMAP3430_ISP_CSI2A_REGS1_END (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F) +#define OMAP3430_ISP_CSIPHY2_END (OMAP3430_ISP_CSIPHY2_BASE + 0x00B) +#define OMAP3630_ISP_CSI2A_REGS2_END (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F) +#define OMAP3630_ISP_CSI2C_REGS1_END (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F) +#define OMAP3630_ISP_CSIPHY1_END (OMAP3630_ISP_CSIPHY1_BASE + 0x00B) +#define OMAP3630_ISP_CSI2C_REGS2_END (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F) + +#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) +#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) +#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000) +#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400) +#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800) +#define OMAP34XX_SR1_BASE 0x480C9000 +#define OMAP34XX_SR2_BASE 0x480CB000 + +#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) + +/* Security */ +#define OMAP34XX_SEC_BASE (L4_34XX_BASE + 0xA0000) +#define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000) +#define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000) + +#endif /* __ASM_ARCH_OMAP3_H */ + diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index c29dee998a7..e1f289748c5 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -16,26 +16,25 @@ #include <linux/io.h> #include <linux/platform_device.h> #include <linux/memblock.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/export.h> #include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/map.h> #include <asm/memblock.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <plat/irqs.h> #include <plat/sram.h> #include <plat/omap-secure.h> #include <plat/mmc.h> -#include <mach/hardware.h> -#include <mach/omap-wakeupgen.h> +#include "omap-wakeupgen.h" +#include "soc.h" #include "common.h" #include "hsmmc.h" #include "omap4-sar-layout.h" -#include <linux/export.h> #ifdef CONFIG_CACHE_L2X0 static void __iomem *l2cache_base; @@ -171,7 +170,10 @@ static int __init omap_l2_cache_init(void) /* Enable PL310 L2 Cache controller */ omap_smc1(0x102, 0x1); - l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); + if (of_have_populated_dt()) + l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); + else + l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); /* * Override default outer_cache.disable with a OMAP4 diff --git a/arch/arm/mach-omap2/omap4-keypad.h b/arch/arm/mach-omap2/omap4-keypad.h new file mode 100644 index 00000000000..20de0d5a7e7 --- /dev/null +++ b/arch/arm/mach-omap2/omap4-keypad.h @@ -0,0 +1,8 @@ +#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H +#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H + +struct omap_board_data; + +extern int omap4_keyboard_init(struct omap4_keypad_platform_data *, + struct omap_board_data *); +#endif diff --git a/arch/arm/mach-omap2/omap44xx.h b/arch/arm/mach-omap2/omap44xx.h new file mode 100644 index 00000000000..43b927b2e2e --- /dev/null +++ b/arch/arm/mach-omap2/omap44xx.h @@ -0,0 +1,62 @@ +/*: + * Address mappings and base address for OMAP4 interconnects + * and peripherals. + * + * Copyright (C) 2009 Texas Instruments + * + * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARCH_OMAP44XX_H +#define __ASM_ARCH_OMAP44XX_H + +/* + * Please place only base defines here and put the rest in device + * specific headers. + */ +#define L4_44XX_BASE 0x4a000000 +#define L4_WK_44XX_BASE 0x4a300000 +#define L4_PER_44XX_BASE 0x48000000 +#define L4_EMU_44XX_BASE 0x54000000 +#define L3_44XX_BASE 0x44000000 +#define OMAP44XX_EMIF1_BASE 0x4c000000 +#define OMAP44XX_EMIF2_BASE 0x4d000000 +#define OMAP44XX_DMM_BASE 0x4e000000 +#define OMAP4430_32KSYNCT_BASE 0x4a304000 +#define OMAP4430_CM1_BASE 0x4a004000 +#define OMAP4430_CM_BASE OMAP4430_CM1_BASE +#define OMAP4430_CM2_BASE 0x4a008000 +#define OMAP4430_PRM_BASE 0x4a306000 +#define OMAP4430_PRCM_MPU_BASE 0x48243000 +#define OMAP44XX_GPMC_BASE 0x50000000 +#define OMAP443X_SCM_BASE 0x4a002000 +#define OMAP443X_CTRL_BASE 0x4a100000 +#define OMAP44XX_IC_BASE 0x48200000 +#define OMAP44XX_IVA_INTC_BASE 0x40000000 +#define IRQ_SIR_IRQ 0x0040 +#define OMAP44XX_GIC_DIST_BASE 0x48241000 +#define OMAP44XX_GIC_CPU_BASE 0x48240100 +#define OMAP44XX_IRQ_GIC_START 32 +#define OMAP44XX_SCU_BASE 0x48240000 +#define OMAP44XX_LOCAL_TWD_BASE 0x48240600 +#define OMAP44XX_L2CACHE_BASE 0x48242000 +#define OMAP44XX_WKUPGEN_BASE 0x48281000 +#define OMAP44XX_MCPDM_BASE 0x40132000 +#define OMAP44XX_SAR_RAM_BASE 0x4a326000 + +#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) +#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) + +#define OMAP4_MMU1_BASE 0x55082000 +#define OMAP4_MMU2_BASE 0x4A066000 + +#define OMAP44XX_USBTLL_BASE (L4_44XX_BASE + 0x62000) +#define OMAP44XX_UHH_CONFIG_BASE (L4_44XX_BASE + 0x64000) +#define OMAP44XX_HSUSB_OHCI_BASE (L4_44XX_BASE + 0x64800) +#define OMAP44XX_HSUSB_EHCI_BASE (L4_44XX_BASE + 0x64C00) + +#endif /* __ASM_ARCH_OMAP44XX_H */ + diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h new file mode 100644 index 00000000000..a2582bb3cab --- /dev/null +++ b/arch/arm/mach-omap2/omap54xx.h @@ -0,0 +1,32 @@ +/*: + * Address mappings and base address for OMAP5 interconnects + * and peripherals. + * + * Copyright (C) 2012 Texas Instruments + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * Sricharan <r.sricharan@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_SOC_OMAP54XX_H +#define __ASM_SOC_OMAP54XX_H + +/* + * Please place only base defines here and put the rest in device + * specific headers. + */ +#define L4_54XX_BASE 0x4a000000 +#define L4_WK_54XX_BASE 0x4ae00000 +#define L4_PER_54XX_BASE 0x48000000 +#define L3_54XX_BASE 0x44000000 +#define OMAP54XX_32KSYNCT_BASE 0x4ae04000 +#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 +#define OMAP54XX_CM_CORE_BASE 0x4a008000 +#define OMAP54XX_PRM_BASE 0x4ae06000 +#define OMAP54XX_PRCM_MPU_BASE 0x48243000 +#define OMAP54XX_SCM_BASE 0x4a002000 +#define OMAP54XX_CTRL_BASE 0x4a002800 + +#endif /* __ASM_SOC_OMAP555554XX_H */ diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 37afbd173c2..00c006686b0 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -139,18 +139,20 @@ #include <linux/slab.h> #include <linux/bootmem.h> -#include "common.h" -#include <plat/cpu.h> -#include "clockdomain.h" -#include "powerdomain.h" #include <plat/clock.h> #include <plat/omap_hwmod.h> #include <plat/prcm.h> +#include "soc.h" +#include "common.h" +#include "clockdomain.h" +#include "powerdomain.h" #include "cm2xxx_3xxx.h" #include "cminst44xx.h" +#include "cm33xx.h" #include "prm2xxx_3xxx.h" #include "prm44xx.h" +#include "prm33xx.h" #include "prminst44xx.h" #include "mux.h" #include "pm.h" @@ -868,6 +870,26 @@ static void _omap4_enable_module(struct omap_hwmod *oh) } /** + * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX + * @oh: struct omap_hwmod * + * + * Enables the PRCM module mode related to the hwmod @oh. + * No return value. + */ +static void _am33xx_enable_module(struct omap_hwmod *oh) +{ + if (!oh->clkdm || !oh->prcm.omap4.modulemode) + return; + + pr_debug("omap_hwmod: %s: %s: %d\n", + oh->name, __func__, oh->prcm.omap4.modulemode); + + am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); +} + +/** * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 * @oh: struct omap_hwmod * * @@ -894,6 +916,31 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh) } /** + * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX + * @oh: struct omap_hwmod * + * + * Wait for a module @oh to enter slave idle. Returns 0 if the module + * does not have an IDLEST bit or if the module successfully enters + * slave idle; otherwise, pass along the return value of the + * appropriate *_cm*_wait_module_idle() function. + */ +static int _am33xx_wait_target_disable(struct omap_hwmod *oh) +{ + if (!oh) + return -EINVAL; + + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return 0; + + if (oh->flags & HWMOD_NO_IDLEST) + return 0; + + return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); +} + +/** * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh * @oh: struct omap_hwmod *oh * @@ -1438,8 +1485,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) * Return the bit position of the reset line that match the * input name. Return -ENOENT if not found. */ -static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, - struct omap_hwmod_rst_info *ohri) +static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, + struct omap_hwmod_rst_info *ohri) { int i; @@ -1475,7 +1522,7 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, static int _assert_hardreset(struct omap_hwmod *oh, const char *name) { struct omap_hwmod_rst_info ohri; - u8 ret = -EINVAL; + int ret = -EINVAL; if (!oh) return -EINVAL; @@ -1484,7 +1531,7 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name) return -ENOSYS; ret = _lookup_hardreset(oh, name, &ohri); - if (IS_ERR_VALUE(ret)) + if (ret < 0) return ret; ret = soc_ops.assert_hardreset(oh, &ohri); @@ -1542,7 +1589,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) static int _read_hardreset(struct omap_hwmod *oh, const char *name) { struct omap_hwmod_rst_info ohri; - u8 ret = -EINVAL; + int ret = -EINVAL; if (!oh) return -EINVAL; @@ -1551,7 +1598,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) return -ENOSYS; ret = _lookup_hardreset(oh, name, &ohri); - if (IS_ERR_VALUE(ret)) + if (ret < 0) return ret; return soc_ops.is_hardreset_asserted(oh, &ohri); @@ -1614,6 +1661,36 @@ static int _omap4_disable_module(struct omap_hwmod *oh) } /** + * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX + * @oh: struct omap_hwmod * + * + * Disable the PRCM module mode related to the hwmod @oh. + * Return EINVAL if the modulemode is not supported and 0 in case of success. + */ +static int _am33xx_disable_module(struct omap_hwmod *oh) +{ + int v; + + if (!oh->clkdm || !oh->prcm.omap4.modulemode) + return -EINVAL; + + pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); + + am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); + + if (_are_any_hardreset_lines_asserted(oh)) + return 0; + + v = _am33xx_wait_target_disable(oh); + if (v) + pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", + oh->name); + + return 0; +} + +/** * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit * @oh: struct omap_hwmod * * @@ -1641,8 +1718,8 @@ static int _ocp_softreset(struct omap_hwmod *oh) /* clocks must be on for this operation */ if (oh->_state != _HWMOD_STATE_ENABLED) { - pr_warning("omap_hwmod: %s: reset can only be entered from " - "enabled state\n", oh->name); + pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", + oh->name); return -EINVAL; } @@ -2549,6 +2626,33 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh) } /** + * _am33xx_wait_target_ready - wait for a module to leave slave idle + * @oh: struct omap_hwmod * + * + * Wait for a module @oh to leave slave idle. Returns 0 if the module + * does not have an IDLEST bit or if the module successfully leaves + * slave idle; otherwise, pass along the return value of the + * appropriate *_cm*_wait_module_ready() function. + */ +static int _am33xx_wait_target_ready(struct omap_hwmod *oh) +{ + if (!oh || !oh->clkdm) + return -EINVAL; + + if (oh->flags & HWMOD_NO_IDLEST) + return 0; + + if (!_find_mpu_rt_port(oh)) + return 0; + + /* XXX check module SIDLEMODE, hardreset status */ + + return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); +} + +/** * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args * @oh: struct omap_hwmod * to assert hardreset * @ohri: hardreset line data @@ -2679,6 +2783,72 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, oh->prcm.omap4.rstctrl_offs); } +/** + * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args + * @oh: struct omap_hwmod * to assert hardreset + * @ohri: hardreset line data + * + * Call am33xx_prminst_assert_hardreset() with parameters extracted + * from the hwmod @oh and the hardreset line data @ohri. Only + * intended for use as an soc_ops function pointer. Passes along the + * return value from am33xx_prminst_assert_hardreset(). XXX This + * function is scheduled for removal when the PRM code is moved into + * drivers/. + */ +static int _am33xx_assert_hardreset(struct omap_hwmod *oh, + struct omap_hwmod_rst_info *ohri) + +{ + return am33xx_prm_assert_hardreset(ohri->rst_shift, + oh->clkdm->pwrdm.ptr->prcm_offs, + oh->prcm.omap4.rstctrl_offs); +} + +/** + * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args + * @oh: struct omap_hwmod * to deassert hardreset + * @ohri: hardreset line data + * + * Call am33xx_prminst_deassert_hardreset() with parameters extracted + * from the hwmod @oh and the hardreset line data @ohri. Only + * intended for use as an soc_ops function pointer. Passes along the + * return value from am33xx_prminst_deassert_hardreset(). XXX This + * function is scheduled for removal when the PRM code is moved into + * drivers/. + */ +static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, + struct omap_hwmod_rst_info *ohri) +{ + if (ohri->st_shift) + pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", + oh->name, ohri->name); + + return am33xx_prm_deassert_hardreset(ohri->rst_shift, + oh->clkdm->pwrdm.ptr->prcm_offs, + oh->prcm.omap4.rstctrl_offs, + oh->prcm.omap4.rstst_offs); +} + +/** + * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args + * @oh: struct omap_hwmod * to test hardreset + * @ohri: hardreset line data + * + * Call am33xx_prminst_is_hardreset_asserted() with parameters + * extracted from the hwmod @oh and the hardreset line data @ohri. + * Only intended for use as an soc_ops function pointer. Passes along + * the return value from am33xx_prminst_is_hardreset_asserted(). XXX + * This function is scheduled for removal when the PRM code is moved + * into drivers/. + */ +static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, + struct omap_hwmod_rst_info *ohri) +{ + return am33xx_prm_is_hardreset_asserted(ohri->rst_shift, + oh->clkdm->pwrdm.ptr->prcm_offs, + oh->prcm.omap4.rstctrl_offs); +} + /* Public functions */ u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) @@ -3159,6 +3329,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) } /** + * omap_hwmod_fill_dma_resources - fill struct resource array with dma data + * @oh: struct omap_hwmod * + * @res: pointer to the array of struct resource to fill + * + * Fill the struct resource array @res with dma resource data from the + * omap_hwmod @oh. Intended to be called by code that registers + * omap_devices. See also omap_hwmod_count_resources(). Returns the + * number of array elements filled. + */ +int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) +{ + int i, sdma_reqs_cnt; + int r = 0; + + sdma_reqs_cnt = _count_sdma_reqs(oh); + for (i = 0; i < sdma_reqs_cnt; i++) { + (res + r)->name = (oh->sdma_reqs + i)->name; + (res + r)->start = (oh->sdma_reqs + i)->dma_req; + (res + r)->end = (oh->sdma_reqs + i)->dma_req; + (res + r)->flags = IORESOURCE_DMA; + r++; + } + + return r; +} + +/** * omap_hwmod_get_resource_byname - fetch IP block integration data by name * @oh: struct omap_hwmod * to operate on * @type: one of the IORESOURCE_* constants from include/linux/ioport.h @@ -3678,6 +3875,14 @@ void __init omap_hwmod_init(void) soc_ops.deassert_hardreset = _omap4_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; soc_ops.init_clkdm = _init_clkdm; + } else if (soc_is_am33xx()) { + soc_ops.enable_module = _am33xx_enable_module; + soc_ops.disable_module = _am33xx_disable_module; + soc_ops.wait_target_ready = _am33xx_wait_target_ready; + soc_ops.assert_hardreset = _am33xx_assert_hardreset; + soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; + soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; + soc_ops.init_clkdm = _init_clkdm; } else { WARN(1, "omap_hwmod: unknown SoC type\n"); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 50cfab61b0e..10575a1bc1f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -12,17 +12,15 @@ * XXX handle crossbar/shared link difference for L3? * XXX these should be marked initdata for multi-OMAP kernels */ +#include <linux/platform_data/spi-omap2-mcspi.h> + #include <plat/omap_hwmod.h> -#include <mach/irqs.h> -#include <plat/cpu.h> #include <plat/dma.h> #include <plat/serial.h> #include <plat/i2c.h> -#include <plat/gpio.h> -#include <plat/mcspi.h> #include <plat/dmtimer.h> -#include <plat/l3_2xxx.h> -#include <plat/l4_2xxx.h> +#include "l3_2xxx.h" +#include "l4_2xxx.h" #include <plat/mmc.h> #include "omap_hwmod_common_data.h" @@ -162,9 +160,9 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { /* mailbox */ static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { - { .name = "dsp", .irq = 26 }, - { .name = "iva", .irq = 34 }, - { .irq = -1 } + { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, + { .name = "iva", .irq = 34 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2420_mailbox_hwmod = { @@ -199,9 +197,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { /* mcbsp1 */ static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .irq = -1 } + { .name = "tx", .irq = 59 + OMAP_INTC_START, }, + { .name = "rx", .irq = 60 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2420_mcbsp1_hwmod = { @@ -225,9 +223,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { /* mcbsp2 */ static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .irq = -1 } + { .name = "tx", .irq = 62 + OMAP_INTC_START, }, + { .name = "rx", .irq = 63 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2420_mcbsp2_hwmod = { @@ -265,8 +263,8 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = { /* msdi1 */ static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = { - { .irq = 83 }, - { .irq = -1 } + { .irq = 83 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 58b5bc196d3..60de70feeae 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -12,21 +12,19 @@ * XXX handle crossbar/shared link difference for L3? * XXX these should be marked initdata for multi-OMAP kernels */ +#include <linux/platform_data/asoc-ti-mcbsp.h> +#include <linux/platform_data/spi-omap2-mcspi.h> + #include <plat/omap_hwmod.h> -#include <mach/irqs.h> -#include <plat/cpu.h> #include <plat/dma.h> #include <plat/serial.h> #include <plat/i2c.h> -#include <plat/gpio.h> -#include <plat/mcbsp.h> -#include <plat/mcspi.h> #include <plat/dmtimer.h> #include <plat/mmc.h> -#include <plat/l3_2xxx.h> +#include "l3_2xxx.h" +#include "soc.h" #include "omap_hwmod_common_data.h" - #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "wd_timer.h" @@ -133,8 +131,8 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { /* gpio5 */ static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { - { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ - { .irq = -1 } + { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */ + { .irq = -1 }, }; static struct omap_hwmod omap2430_gpio5_hwmod = { @@ -173,8 +171,8 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { /* mailbox */ static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { - { .irq = 26 }, - { .irq = -1 } + { .irq = 26 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_mailbox_hwmod = { @@ -195,8 +193,8 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { /* mcspi3 */ static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { - { .irq = 91 }, - { .irq = -1 } + { .irq = 91 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { @@ -250,9 +248,9 @@ static struct omap_hwmod_class usbotg_class = { /* usb_otg_hs */ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { - { .name = "mc", .irq = 92 }, - { .name = "dma", .irq = 93 }, - { .irq = -1 } + { .name = "mc", .irq = 92 + OMAP_INTC_START, }, + { .name = "dma", .irq = 93 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_usbhsotg_hwmod = { @@ -303,11 +301,11 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { /* mcbsp1 */ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .name = "ovr", .irq = 61 }, - { .name = "common", .irq = 64 }, - { .irq = -1 } + { .name = "tx", .irq = 59 + OMAP_INTC_START, }, + { .name = "rx", .irq = 60 + OMAP_INTC_START, }, + { .name = "ovr", .irq = 61 + OMAP_INTC_START, }, + { .name = "common", .irq = 64 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_mcbsp1_hwmod = { @@ -331,10 +329,10 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { /* mcbsp2 */ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .name = "common", .irq = 16 }, - { .irq = -1 } + { .name = "tx", .irq = 62 + OMAP_INTC_START, }, + { .name = "rx", .irq = 63 + OMAP_INTC_START, }, + { .name = "common", .irq = 16 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_mcbsp2_hwmod = { @@ -358,10 +356,10 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { /* mcbsp3 */ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { - { .name = "tx", .irq = 89 }, - { .name = "rx", .irq = 90 }, - { .name = "common", .irq = 17 }, - { .irq = -1 } + { .name = "tx", .irq = 89 + OMAP_INTC_START, }, + { .name = "rx", .irq = 90 + OMAP_INTC_START, }, + { .name = "common", .irq = 17 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_mcbsp3_hwmod = { @@ -385,10 +383,10 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { /* mcbsp4 */ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { - { .name = "tx", .irq = 54 }, - { .name = "rx", .irq = 55 }, - { .name = "common", .irq = 18 }, - { .irq = -1 } + { .name = "tx", .irq = 54 + OMAP_INTC_START, }, + { .name = "rx", .irq = 55 + OMAP_INTC_START, }, + { .name = "common", .irq = 18 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { @@ -418,10 +416,10 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { /* mcbsp5 */ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { - { .name = "tx", .irq = 81 }, - { .name = "rx", .irq = 82 }, - { .name = "common", .irq = 19 }, - { .irq = -1 } + { .name = "tx", .irq = 81 + OMAP_INTC_START, }, + { .name = "rx", .irq = 82 + OMAP_INTC_START, }, + { .name = "common", .irq = 19 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { @@ -468,8 +466,8 @@ static struct omap_hwmod_class omap2430_mmc_class = { /* MMC/SD/SDIO1 */ static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { - { .irq = 83 }, - { .irq = -1 } + { .irq = 83 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { @@ -509,8 +507,8 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { /* MMC/SD/SDIO2 */ static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { - { .irq = 86 }, - { .irq = -1 } + { .irq = 86 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index 102d76e9e9e..8851bbb6bb2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c @@ -13,9 +13,7 @@ #include <plat/serial.h> #include <plat/dma.h> #include <plat/common.h> -#include <plat/hdq1w.h> - -#include <mach/irqs.h> +#include "hdq1w.h" #include "omap_hwmod_common_data.h" @@ -182,126 +180,126 @@ struct omap_hwmod_class iva_hwmod_class = { /* Common MPU IRQ line data */ struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = { - { .irq = 37, }, - { .irq = -1 } + { .irq = 37 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = { - { .irq = 38, }, - { .irq = -1 } + { .irq = 38 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = { - { .irq = 39, }, - { .irq = -1 } + { .irq = 39 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = { - { .irq = 40, }, - { .irq = -1 } + { .irq = 40 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = { - { .irq = 41, }, - { .irq = -1 } + { .irq = 41 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = { - { .irq = 42, }, - { .irq = -1 } + { .irq = 42 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = { - { .irq = 43, }, - { .irq = -1 } + { .irq = 43 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = { - { .irq = 44, }, - { .irq = -1 } + { .irq = 44 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = { - { .irq = 45, }, - { .irq = -1 } + { .irq = 45 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = { - { .irq = 46, }, - { .irq = -1 } + { .irq = 46 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = { - { .irq = 47, }, - { .irq = -1 } + { .irq = 47 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = { - { .irq = INT_24XX_UART1_IRQ, }, - { .irq = -1 } + { .irq = 72 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = { - { .irq = INT_24XX_UART2_IRQ, }, - { .irq = -1 } + { .irq = 73 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = { - { .irq = INT_24XX_UART3_IRQ, }, - { .irq = -1 } + { .irq = 74 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_dispc_irqs[] = { - { .irq = 25 }, - { .irq = -1 } + { .irq = 25 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = { - { .irq = INT_24XX_I2C1_IRQ, }, - { .irq = -1 } + { .irq = 56 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = { - { .irq = INT_24XX_I2C2_IRQ, }, - { .irq = -1 } + { .irq = 57 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_gpio1_irqs[] = { - { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ - { .irq = -1 } + { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_gpio2_irqs[] = { - { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ - { .irq = -1 } + { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_gpio3_irqs[] = { - { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ - { .irq = -1 } + { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_gpio4_irqs[] = { - { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ - { .irq = -1 } + { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { - { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ - { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ - { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ - { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ - { .irq = -1 } + { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */ + { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ + { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ + { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = { - { .irq = 65 }, - { .irq = -1 } + { .irq = 65 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { - { .irq = 66 }, - { .irq = -1 } + { .irq = 66 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { @@ -320,7 +318,7 @@ struct omap_hwmod_class omap2_hdq1w_class = { }; struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { - { .irq = 58, }, - { .irq = -1 } + { .irq = 58 + OMAP_INTC_START, }, + { .irq = -1 }, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 5178e40e84f..f853a0b1d5c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -15,8 +15,8 @@ #include <plat/omap_hwmod.h> #include <plat/serial.h> -#include <plat/l3_2xxx.h> -#include <plat/l4_2xxx.h> +#include "l3_2xxx.h" +#include "l4_2xxx.h" #include "omap_hwmod_common_data.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index afad69c6ba6..feeb401cf87 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -10,12 +10,10 @@ */ #include <plat/omap_hwmod.h> #include <plat/serial.h> -#include <plat/gpio.h> +#include <linux/platform_data/gpio-omap.h> #include <plat/dma.h> #include <plat/dmtimer.h> -#include <plat/mcspi.h> - -#include <mach/irqs.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include "omap_hwmod_common_data.h" #include "cm-regbits-24xx.h" @@ -23,8 +21,8 @@ #include "wd_timer.h" struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { - { .irq = 48, }, - { .irq = -1 } + { .irq = 48 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c new file mode 100644 index 00000000000..59d5c1cd316 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -0,0 +1,3381 @@ +/* + * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips + * + * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is automatically generated from the AM33XX hardware databases. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <plat/omap_hwmod.h> +#include <plat/cpu.h> +#include <linux/platform_data/gpio-omap.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <plat/dma.h> +#include <plat/mmc.h> +#include <plat/i2c.h> + +#include "omap_hwmod_common_data.h" + +#include "control.h" +#include "cm33xx.h" +#include "prm33xx.h" +#include "prm-regbits-33xx.h" + +/* + * IP blocks + */ + +/* + * 'emif_fw' class + * instance(s): emif_fw + */ +static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = { + .name = "emif_fw", +}; + +/* emif_fw */ +static struct omap_hwmod am33xx_emif_fw_hwmod = { + .name = "emif_fw", + .class = &am33xx_emif_fw_hwmod_class, + .clkdm_name = "l4fw_clkdm", + .main_clk = "l4fw_gclk", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'emif' class + * instance(s): emif + */ +static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { + .rev_offs = 0x0000, +}; + +static struct omap_hwmod_class am33xx_emif_hwmod_class = { + .name = "emif", + .sysc = &am33xx_emif_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_emif_irqs[] = { + { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +/* emif */ +static struct omap_hwmod am33xx_emif_hwmod = { + .name = "emif", + .class = &am33xx_emif_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_emif_irqs, + .main_clk = "dpll_ddr_m2_div2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'l3' class + * instance(s): l3_main, l3_s, l3_instr + */ +static struct omap_hwmod_class am33xx_l3_hwmod_class = { + .name = "l3", +}; + +/* l3_main (l3_fast) */ +static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = { + { .name = "l3debug", .irq = 9 + OMAP_INTC_START, }, + { .name = "l3appint", .irq = 10 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_l3_main_hwmod = { + .name = "l3_main", + .class = &am33xx_l3_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_l3_main_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* l3_s */ +static struct omap_hwmod am33xx_l3_s_hwmod = { + .name = "l3_s", + .class = &am33xx_l3_hwmod_class, + .clkdm_name = "l3s_clkdm", +}; + +/* l3_instr */ +static struct omap_hwmod am33xx_l3_instr_hwmod = { + .name = "l3_instr", + .class = &am33xx_l3_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'l4' class + * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw + */ +static struct omap_hwmod_class am33xx_l4_hwmod_class = { + .name = "l4", +}; + +/* l4_ls */ +static struct omap_hwmod am33xx_l4_ls_hwmod = { + .name = "l4_ls", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* l4_hs */ +static struct omap_hwmod am33xx_l4_hs_hwmod = { + .name = "l4_hs", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4hs_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l4hs_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + + +/* l4_wkup */ +static struct omap_hwmod am33xx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* l4_fw */ +static struct omap_hwmod am33xx_l4_fw_hwmod = { + .name = "l4_fw", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4fw_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mpu' class + */ +static struct omap_hwmod_class am33xx_mpu_hwmod_class = { + .name = "mpu", +}; + +/* mpu */ +static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = { + { .name = "emuint", .irq = 0 + OMAP_INTC_START, }, + { .name = "commtx", .irq = 1 + OMAP_INTC_START, }, + { .name = "commrx", .irq = 2 + OMAP_INTC_START, }, + { .name = "bench", .irq = 3 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_mpu_hwmod = { + .name = "mpu", + .class = &am33xx_mpu_hwmod_class, + .clkdm_name = "mpu_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_mpu_irqs, + .main_clk = "dpll_mpu_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'wakeup m3' class + * Wakeup controller sub-system under wakeup domain + */ +static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { + .name = "wkup_m3", +}; + +static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { + { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, +}; + +static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = { + { .name = "txev", .irq = 78 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +/* wkup_m3 */ +static struct omap_hwmod am33xx_wkup_m3_hwmod = { + .name = "wkup_m3", + .class = &am33xx_wkup_m3_hwmod_class, + .clkdm_name = "l4_wkup_aon_clkdm", + .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */ + .mpu_irqs = am33xx_wkup_m3_irqs, + .main_clk = "dpll_core_m4_div2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, + .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .rst_lines = am33xx_wkup_m3_resets, + .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), +}; + +/* + * 'pru-icss' class + * Programmable Real-Time Unit and Industrial Communication Subsystem + */ +static struct omap_hwmod_class am33xx_pruss_hwmod_class = { + .name = "pruss", +}; + +static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { + { .name = "pruss", .rst_shift = 1 }, +}; + +static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = { + { .name = "evtout0", .irq = 20 + OMAP_INTC_START, }, + { .name = "evtout1", .irq = 21 + OMAP_INTC_START, }, + { .name = "evtout2", .irq = 22 + OMAP_INTC_START, }, + { .name = "evtout3", .irq = 23 + OMAP_INTC_START, }, + { .name = "evtout4", .irq = 24 + OMAP_INTC_START, }, + { .name = "evtout5", .irq = 25 + OMAP_INTC_START, }, + { .name = "evtout6", .irq = 26 + OMAP_INTC_START, }, + { .name = "evtout7", .irq = 27 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +/* pru-icss */ +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod am33xx_pruss_hwmod = { + .name = "pruss", + .class = &am33xx_pruss_hwmod_class, + .clkdm_name = "pruss_ocp_clkdm", + .mpu_irqs = am33xx_pruss_irqs, + .main_clk = "pruss_ocp_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET, + .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .rst_lines = am33xx_pruss_resets, + .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), +}; + +/* gfx */ +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod_class am33xx_gfx_hwmod_class = { + .name = "gfx", +}; + +static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { + { .name = "gfx", .rst_shift = 0 }, +}; + +static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = { + { .name = "gfxint", .irq = 37 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_gfx_hwmod = { + .name = "gfx", + .class = &am33xx_gfx_hwmod_class, + .clkdm_name = "gfx_l3_clkdm", + .mpu_irqs = am33xx_gfx_irqs, + .main_clk = "gfx_fck_div_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, + .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .rst_lines = am33xx_gfx_resets, + .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), +}; + +/* + * 'prcm' class + * power and reset manager (whole prcm infrastructure) + */ +static struct omap_hwmod_class am33xx_prcm_hwmod_class = { + .name = "prcm", +}; + +/* prcm */ +static struct omap_hwmod am33xx_prcm_hwmod = { + .name = "prcm", + .class = &am33xx_prcm_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", +}; + +/* + * 'adc/tsc' class + * TouchScreen Controller (Anolog-To-Digital Converter) + */ +static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x10, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { + .name = "adc_tsc", + .sysc = &am33xx_adc_tsc_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = { + { .irq = 16 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_adc_tsc_hwmod = { + .name = "adc_tsc", + .class = &am33xx_adc_tsc_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_adc_tsc_irqs, + .main_clk = "adc_tsc_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * Modules omap_hwmod structures + * + * The following IPs are excluded for the moment because: + * - They do not need an explicit SW control using omap_hwmod API. + * - They still need to be validated with the driver + * properly adapted to omap_hwmod / omap_device + * + * - cEFUSE (doesn't fall under any ocp_if) + * - clkdiv32k + * - debugss + * - ocmc ram + * - ocp watch point + * - aes0 + * - sha0 + */ +#if 0 +/* + * 'cefuse' class + */ +static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { + .name = "cefuse", +}; + +static struct omap_hwmod am33xx_cefuse_hwmod = { + .name = "cefuse", + .class = &am33xx_cefuse_hwmod_class, + .clkdm_name = "l4_cefuse_clkdm", + .main_clk = "cefuse_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'clkdiv32k' class + */ +static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { + .name = "clkdiv32k", +}; + +static struct omap_hwmod am33xx_clkdiv32k_hwmod = { + .name = "clkdiv32k", + .class = &am33xx_clkdiv32k_hwmod_class, + .clkdm_name = "clk_24mhz_clkdm", + .main_clk = "clkdiv32k_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'debugss' class + * debug sub system + */ +static struct omap_hwmod_class am33xx_debugss_hwmod_class = { + .name = "debugss", +}; + +static struct omap_hwmod am33xx_debugss_hwmod = { + .name = "debugss", + .class = &am33xx_debugss_hwmod_class, + .clkdm_name = "l3_aon_clkdm", + .main_clk = "debugss_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ocmcram */ +static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { + .name = "ocmcram", +}; + +static struct omap_hwmod am33xx_ocmcram_hwmod = { + .name = "ocmcram", + .class = &am33xx_ocmcram_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ocpwp */ +static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { + .name = "ocpwp", +}; + +static struct omap_hwmod am33xx_ocpwp_hwmod = { + .name = "ocpwp", + .class = &am33xx_ocpwp_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'aes' class + */ +static struct omap_hwmod_class am33xx_aes_hwmod_class = { + .name = "aes", +}; + +static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { + { .irq = 102 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_aes0_hwmod = { + .name = "aes0", + .class = &am33xx_aes_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_aes0_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* sha0 */ +static struct omap_hwmod_class am33xx_sha0_hwmod_class = { + .name = "sha0", +}; + +static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { + { .irq = 108 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_sha0_hwmod = { + .name = "sha0", + .class = &am33xx_sha0_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_sha0_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +#endif + +/* 'smartreflex' class */ +static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { + .name = "smartreflex", +}; + +/* smartreflex0 */ +static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = { + { .irq = 120 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_smartreflex0_hwmod = { + .name = "smartreflex0", + .class = &am33xx_smartreflex_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_smartreflex0_irqs, + .main_clk = "smartreflex0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* smartreflex1 */ +static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = { + { .irq = 121 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_smartreflex1_hwmod = { + .name = "smartreflex1", + .class = &am33xx_smartreflex_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_smartreflex1_irqs, + .main_clk = "smartreflex1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'control' module class + */ +static struct omap_hwmod_class am33xx_control_hwmod_class = { + .name = "control", +}; + +static struct omap_hwmod_irq_info am33xx_control_irqs[] = { + { .irq = 8 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_control_hwmod = { + .name = "control", + .class = &am33xx_control_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_control_irqs, + .main_clk = "dpll_core_m4_div2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'cpgmac' class + * cpsw/cpgmac sub system + */ +static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x8, + .syss_offs = 0x4, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | + MSTANDBY_NO), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { + .name = "cpgmac0", + .sysc = &am33xx_cpgmac_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = { + { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, }, + { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, }, + { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, }, + { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_cpgmac0_hwmod = { + .name = "cpgmac0", + .class = &am33xx_cpgmac0_hwmod_class, + .clkdm_name = "cpsw_125mhz_clkdm", + .mpu_irqs = am33xx_cpgmac0_irqs, + .main_clk = "cpsw_125mhz_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * dcan class + */ +static struct omap_hwmod_class am33xx_dcan_hwmod_class = { + .name = "d_can", +}; + +/* dcan0 */ +static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = { + { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, }, + { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_dcan0_hwmod = { + .name = "d_can0", + .class = &am33xx_dcan_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_dcan0_irqs, + .main_clk = "dcan0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* dcan1 */ +static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = { + { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, }, + { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, }, + { .irq = -1 }, +}; +static struct omap_hwmod am33xx_dcan1_hwmod = { + .name = "d_can1", + .class = &am33xx_dcan_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_dcan1_irqs, + .main_clk = "dcan1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* elm */ +static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_elm_hwmod_class = { + .name = "elm", + .sysc = &am33xx_elm_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_elm_irqs[] = { + { .irq = 4 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_elm_hwmod = { + .name = "elm", + .class = &am33xx_elm_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_elm_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2 + */ +static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_epwmss_hwmod_class = { + .name = "epwmss", + .sysc = &am33xx_epwmss_sysc, +}; + +/* ehrpwm0 */ +static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = { + { .name = "int", .irq = 86 + OMAP_INTC_START, }, + { .name = "tzint", .irq = 58 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ehrpwm0_hwmod = { + .name = "ehrpwm0", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ehrpwm0_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ehrpwm1 */ +static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = { + { .name = "int", .irq = 87 + OMAP_INTC_START, }, + { .name = "tzint", .irq = 59 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ehrpwm1_hwmod = { + .name = "ehrpwm1", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ehrpwm1_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ehrpwm2 */ +static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = { + { .name = "int", .irq = 39 + OMAP_INTC_START, }, + { .name = "tzint", .irq = 60 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ehrpwm2_hwmod = { + .name = "ehrpwm2", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ehrpwm2_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ecap0 */ +static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { + { .irq = 31 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ecap0_hwmod = { + .name = "ecap0", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ecap0_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ecap1 */ +static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = { + { .irq = 47 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ecap1_hwmod = { + .name = "ecap1", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ecap1_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ecap2 */ +static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = { + { .irq = 61 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ecap2_hwmod = { + .name = "ecap2", + .mpu_irqs = am33xx_ecap2_irqs, + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'gpio' class: for gpio 0,1,2,3 + */ +static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &am33xx_gpio_sysc, + .rev = 2, +}; + +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +/* gpio0 */ +static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { + { .role = "dbclk", .clk = "gpio0_dbclk" }, +}; + +static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = { + { .irq = 96 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_gpio0_hwmod = { + .name = "gpio1", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = am33xx_gpio0_irqs, + .main_clk = "dpll_core_m4_div2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio0_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio1 */ +static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = { + { .irq = 98 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbclk" }, +}; + +static struct omap_hwmod am33xx_gpio1_hwmod = { + .name = "gpio2", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = am33xx_gpio1_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio2 */ +static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = { + { .irq = 32 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbclk" }, +}; + +static struct omap_hwmod am33xx_gpio2_hwmod = { + .name = "gpio3", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = am33xx_gpio2_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio3 */ +static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = { + { .irq = 62 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbclk" }, +}; + +static struct omap_hwmod am33xx_gpio3_hwmod = { + .name = "gpio4", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = am33xx_gpio3_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpmc */ +static struct omap_hwmod_class_sysconfig gpmc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &gpmc_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = { + { .irq = 100 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_gpmc_hwmod = { + .name = "gpmc", + .class = &am33xx_gpmc_hwmod_class, + .clkdm_name = "l3s_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_gpmc_irqs, + .main_clk = "l3s_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'i2c' class */ +static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { + .sysc_offs = 0x0010, + .syss_offs = 0x0090, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &am33xx_i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_2, + .reset = &omap_i2c_reset, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr = { + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE | + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE, +}; + +/* i2c1 */ +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = 70 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info i2c1_edma_reqs[] = { + { .name = "tx", .dma_req = 0, }, + { .name = "rx", .dma_req = 0, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_i2c1_hwmod = { + .name = "i2c1", + .class = &i2c_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = i2c1_mpu_irqs, + .sdma_reqs = i2c1_edma_reqs, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "dpll_per_m2_div4_wkupdm_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c1 */ +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = 71 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info i2c2_edma_reqs[] = { + { .name = "tx", .dma_req = 0, }, + { .name = "rx", .dma_req = 0, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_i2c2_hwmod = { + .name = "i2c2", + .class = &i2c_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = i2c2_mpu_irqs, + .sdma_reqs = i2c2_edma_reqs, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c3 */ +static struct omap_hwmod_dma_info i2c3_edma_reqs[] = { + { .name = "tx", .dma_req = 0, }, + { .name = "rx", .dma_req = 0, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { + { .irq = 30 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_i2c3_hwmod = { + .name = "i2c3", + .class = &i2c_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = i2c3_mpu_irqs, + .sdma_reqs = i2c3_edma_reqs, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + + +/* lcdc */ +static struct omap_hwmod_class_sysconfig lcdc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x54, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { + .name = "lcdc", + .sysc = &lcdc_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = { + { .irq = 36 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_lcdc_hwmod = { + .name = "lcdc", + .class = &am33xx_lcdc_hwmod_class, + .clkdm_name = "lcdc_clkdm", + .mpu_irqs = am33xx_lcdc_irqs, + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .main_clk = "lcd_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors using a + * queued mailbox-interrupt mechanism. + */ +static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &am33xx_mailbox_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = { + { .irq = 77 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_mailbox_hwmod = { + .name = "mailbox", + .class = &am33xx_mailbox_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_mailbox_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mcasp' class + */ +static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { + .name = "mcasp", + .sysc = &am33xx_mcasp_sysc, +}; + +/* mcasp0 */ +static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = { + { .name = "ax", .irq = 80 + OMAP_INTC_START, }, + { .name = "ar", .irq = 81 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = { + { .name = "tx", .dma_req = 8, }, + { .name = "rx", .dma_req = 9, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_mcasp0_hwmod = { + .name = "mcasp0", + .class = &am33xx_mcasp_hwmod_class, + .clkdm_name = "l3s_clkdm", + .mpu_irqs = am33xx_mcasp0_irqs, + .sdma_reqs = am33xx_mcasp0_edma_reqs, + .main_clk = "mcasp0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* mcasp1 */ +static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = { + { .name = "ax", .irq = 82 + OMAP_INTC_START, }, + { .name = "ar", .irq = 83 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = { + { .name = "tx", .dma_req = 10, }, + { .name = "rx", .dma_req = 11, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_mcasp1_hwmod = { + .name = "mcasp1", + .class = &am33xx_mcasp_hwmod_class, + .clkdm_name = "l3s_clkdm", + .mpu_irqs = am33xx_mcasp1_irqs, + .sdma_reqs = am33xx_mcasp1_edma_reqs, + .main_clk = "mcasp1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'mmc' class */ +static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_mmc_hwmod_class = { + .name = "mmc", + .sysc = &am33xx_mmc_sysc, +}; + +/* mmc0 */ +static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = { + { .irq = 64 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = { + { .name = "tx", .dma_req = 24, }, + { .name = "rx", .dma_req = 25, }, + { .dma_req = -1 } +}; + +static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod am33xx_mmc0_hwmod = { + .name = "mmc1", + .class = &am33xx_mmc_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_mmc0_irqs, + .sdma_reqs = am33xx_mmc0_edma_reqs, + .main_clk = "mmc_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &am33xx_mmc0_dev_attr, +}; + +/* mmc1 */ +static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = { + { .irq = 28 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = { + { .name = "tx", .dma_req = 2, }, + { .name = "rx", .dma_req = 3, }, + { .dma_req = -1 } +}; + +static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod am33xx_mmc1_hwmod = { + .name = "mmc2", + .class = &am33xx_mmc_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_mmc1_irqs, + .sdma_reqs = am33xx_mmc1_edma_reqs, + .main_clk = "mmc_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &am33xx_mmc1_dev_attr, +}; + +/* mmc2 */ +static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = { + { .irq = 29 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = { + { .name = "tx", .dma_req = 64, }, + { .name = "rx", .dma_req = 65, }, + { .dma_req = -1 } +}; + +static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; +static struct omap_hwmod am33xx_mmc2_hwmod = { + .name = "mmc3", + .class = &am33xx_mmc_hwmod_class, + .clkdm_name = "l3s_clkdm", + .mpu_irqs = am33xx_mmc2_irqs, + .sdma_reqs = am33xx_mmc2_edma_reqs, + .main_clk = "mmc_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &am33xx_mmc2_dev_attr, +}; + +/* + * 'rtc' class + * rtc subsystem + */ +static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { + .rev_offs = 0x0074, + .sysc_offs = 0x0078, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | + SIDLE_SMART | SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class am33xx_rtc_hwmod_class = { + .name = "rtc", + .sysc = &am33xx_rtc_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = { + { .name = "rtcint", .irq = 75 + OMAP_INTC_START, }, + { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_rtc_hwmod = { + .name = "rtc", + .class = &am33xx_rtc_hwmod_class, + .clkdm_name = "l4_rtc_clkdm", + .mpu_irqs = am33xx_rtc_irqs, + .main_clk = "clk_32768_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'spi' class */ +static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0110, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_spi_hwmod_class = { + .name = "mcspi", + .sysc = &am33xx_mcspi_sysc, + .rev = OMAP4_MCSPI_REV, +}; + +/* spi0 */ +static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = { + { .irq = 65 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = { + { .name = "rx0", .dma_req = 17 }, + { .name = "tx0", .dma_req = 16 }, + { .name = "rx1", .dma_req = 19 }, + { .name = "tx1", .dma_req = 18 }, + { .dma_req = -1 } +}; + +static struct omap2_mcspi_dev_attr mcspi_attrib = { + .num_chipselect = 2, +}; +static struct omap_hwmod am33xx_spi0_hwmod = { + .name = "spi0", + .class = &am33xx_spi_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_spi0_irqs, + .sdma_reqs = am33xx_mcspi0_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi_attrib, +}; + +/* spi1 */ +static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = { + { .irq = 125 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = { + { .name = "rx0", .dma_req = 43 }, + { .name = "tx0", .dma_req = 42 }, + { .name = "rx1", .dma_req = 45 }, + { .name = "tx1", .dma_req = 44 }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_spi1_hwmod = { + .name = "spi1", + .class = &am33xx_spi_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_spi1_irqs, + .sdma_reqs = am33xx_mcspi1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi_attrib, +}; + +/* + * 'spinlock' class + * spinlock provides hardware assistance for synchronizing the + * processes running on multiple processors + */ +static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { + .name = "spinlock", +}; + +static struct omap_hwmod am33xx_spinlock_hwmod = { + .name = "spinlock", + .class = &am33xx_spinlock_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'timer 2-7' class */ +static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_timer_hwmod_class = { + .name = "timer", + .sysc = &am33xx_timer_sysc, +}; + +/* timer1 1ms */ +static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { + .name = "timer", + .sysc = &am33xx_timer1ms_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = { + { .irq = 67 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer1_hwmod = { + .name = "timer1", + .class = &am33xx_timer1ms_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_timer1_irqs, + .main_clk = "timer1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = { + { .irq = 68 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer2_hwmod = { + .name = "timer2", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer2_irqs, + .main_clk = "timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = { + { .irq = 69 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer3_hwmod = { + .name = "timer3", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer3_irqs, + .main_clk = "timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = { + { .irq = 92 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer4_hwmod = { + .name = "timer4", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer4_irqs, + .main_clk = "timer4_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = { + { .irq = 93 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer5_hwmod = { + .name = "timer5", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer5_irqs, + .main_clk = "timer5_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = { + { .irq = 94 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer6_hwmod = { + .name = "timer6", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer6_irqs, + .main_clk = "timer6_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = { + { .irq = 95 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer7_hwmod = { + .name = "timer7", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer7_irqs, + .main_clk = "timer7_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* tpcc */ +static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { + .name = "tpcc", +}; + +static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = { + { .name = "edma0", .irq = 12 + OMAP_INTC_START, }, + { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, }, + { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_tpcc_hwmod = { + .name = "tpcc", + .class = &am33xx_tpcc_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_tpcc_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +/* 'tptc' class */ +static struct omap_hwmod_class am33xx_tptc_hwmod_class = { + .name = "tptc", + .sysc = &am33xx_tptc_sysc, +}; + +/* tptc0 */ +static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = { + { .irq = 112 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_tptc0_hwmod = { + .name = "tptc0", + .class = &am33xx_tptc_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_tptc0_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* tptc1 */ +static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = { + { .irq = 113 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_tptc1_hwmod = { + .name = "tptc1", + .class = &am33xx_tptc_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_tptc1_irqs, + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* tptc2 */ +static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = { + { .irq = 114 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_tptc2_hwmod = { + .name = "tptc2", + .class = &am33xx_tptc_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_tptc2_irqs, + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'uart' class */ +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* uart1 */ +static struct omap_hwmod_dma_info uart1_edma_reqs[] = { + { .name = "tx", .dma_req = 26, }, + { .name = "rx", .dma_req = 27, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = { + { .irq = 72 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart1_hwmod = { + .name = "uart1", + .class = &uart_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_uart1_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_wkupdm_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { + { .irq = 73 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart2_hwmod = { + .name = "uart2", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart2_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart3 */ +static struct omap_hwmod_dma_info uart3_edma_reqs[] = { + { .name = "tx", .dma_req = 30, }, + { .name = "rx", .dma_req = 31, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = { + { .irq = 74 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart3_hwmod = { + .name = "uart3", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart3_irqs, + .sdma_reqs = uart3_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = { + { .irq = 44 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart4_hwmod = { + .name = "uart4", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart4_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = { + { .irq = 45 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart5_hwmod = { + .name = "uart5", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart5_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = { + { .irq = 46 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart6_hwmod = { + .name = "uart6", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart6_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'wd_timer' class */ +static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { + .name = "wd_timer", +}; + +/* + * XXX: device.c file uses hardcoded name for watchdog timer + * driver "wd_timer2, so we are also using same name as of now... + */ +static struct omap_hwmod am33xx_wd_timer1_hwmod = { + .name = "wd_timer2", + .class = &am33xx_wd_timer_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .main_clk = "wdt1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'usb_otg' class + * high-speed on-the-go universal serial bus (usb_otg) controller + */ +static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_usbotg_class = { + .name = "usbotg", + .sysc = &am33xx_usbhsotg_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = { + { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, }, + { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, }, + { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, }, + { .irq = -1 + OMAP_INTC_START, }, +}; + +static struct omap_hwmod am33xx_usbss_hwmod = { + .name = "usb_otg_hs", + .class = &am33xx_usbotg_class, + .clkdm_name = "l3s_clkdm", + .mpu_irqs = am33xx_usbss_mpu_irqs, + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .main_clk = "usbotg_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + + +/* + * Interfaces + */ + +/* l4 fw -> emif fw */ +static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = { + .master = &am33xx_l4_fw_hwmod, + .slave = &am33xx_emif_fw_hwmod, + .clk = "l4fw_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { + { + .pa_start = 0x4c000000, + .pa_end = 0x4c000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; +/* l3 main -> emif */ +static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_emif_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_emif_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l3 main */ +static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { + .master = &am33xx_mpu_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "dpll_mpu_m2_ck", + .user = OCP_USER_MPU, +}; + +/* l3 main -> l4 hs */ +static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_l4_hs_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 main -> l3 s */ +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_l3_s_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l4 per/ls */ +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l4_ls_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l4 wkup */ +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l4_wkup_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l4 fw */ +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l4_fw_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 main -> l3 instr */ +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_l3_instr_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> prcm */ +static struct omap_hwmod_ocp_if am33xx_mpu__prcm = { + .master = &am33xx_mpu_hwmod, + .slave = &am33xx_prcm_hwmod, + .clk = "dpll_mpu_m2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l3 main*/ +static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* pru-icss -> l3 main */ +static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { + .master = &am33xx_pruss_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "l3_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* wkup m3 -> l4 wkup */ +static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { + .master = &am33xx_wkup_m3_hwmod, + .slave = &am33xx_l4_wkup_hwmod, + .clk = "dpll_core_m4_div2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gfx -> l3 main */ +static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { + .master = &am33xx_gfx_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "dpll_core_m4_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 wkup -> wkup m3 */ +static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = { + { + .name = "umem", + .pa_start = 0x44d00000, + .pa_end = 0x44d00000 + SZ_16K - 1, + .flags = ADDR_TYPE_RT + }, + { + .name = "dmem", + .pa_start = 0x44d80000, + .pa_end = 0x44d80000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_wkup_m3_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_wkup_m3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 hs -> pru-icss */ +static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = { + { + .pa_start = 0x4a300000, + .pa_end = 0x4a300000 + SZ_512K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { + .master = &am33xx_l4_hs_hwmod, + .slave = &am33xx_pruss_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_pruss_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 main -> gfx */ +static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = { + { + .pa_start = 0x56000000, + .pa_end = 0x56000000 + SZ_16M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_gfx_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_gfx_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 wkup -> smartreflex0 */ +static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = { + { + .pa_start = 0x44e37000, + .pa_end = 0x44e37000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_smartreflex0_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_smartreflex0_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> smartreflex1 */ +static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = { + { + .pa_start = 0x44e39000, + .pa_end = 0x44e39000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_smartreflex1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_smartreflex1_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> control */ +static struct omap_hwmod_addr_space am33xx_control_addrs[] = { + { + .pa_start = 0x44e10000, + .pa_end = 0x44e10000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_control_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_control_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> rtc */ +static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = { + { + .pa_start = 0x44e3e000, + .pa_end = 0x44e3e000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_rtc_hwmod, + .clk = "clkdiv32k_ick", + .addr = am33xx_rtc_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 per/ls -> DCAN0 */ +static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = { + { + .pa_start = 0x481CC000, + .pa_end = 0x481CC000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_dcan0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_dcan0_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> DCAN1 */ +static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = { + { + .pa_start = 0x481D0000, + .pa_end = 0x481D0000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_dcan1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_dcan1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> GPIO2 */ +static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = { + { + .pa_start = 0x4804C000, + .pa_end = 0x4804C000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_gpio1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> gpio3 */ +static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = { + { + .pa_start = 0x481AC000, + .pa_end = 0x481AC000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_gpio2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> gpio4 */ +static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = { + { + .pa_start = 0x481AE000, + .pa_end = 0x481AE000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_gpio3_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> I2C1 */ +static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = { + { + .pa_start = 0x44E0B000, + .pa_end = 0x44E0B000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_i2c1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_i2c1_addr_space, + .user = OCP_USER_MPU, +}; + +/* L4 WKUP -> GPIO1 */ +static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = { + { + .pa_start = 0x44E07000, + .pa_end = 0x44E07000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_gpio0_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_gpio0_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> ADC_TSC */ +static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = { + { + .pa_start = 0x44E0D000, + .pa_end = 0x44E0D000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_adc_tsc_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_adc_tsc_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = { + /* cpsw ss */ + { + .pa_start = 0x4a100000, + .pa_end = 0x4a100000 + SZ_2K - 1, + .flags = ADDR_TYPE_RT, + }, + /* cpsw wr */ + { + .pa_start = 0x4a101200, + .pa_end = 0x4a101200 + SZ_256 - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { + .master = &am33xx_l4_hs_hwmod, + .slave = &am33xx_cpgmac0_hwmod, + .clk = "cpsw_125mhz_gclk", + .addr = am33xx_cpgmac0_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { + { + .pa_start = 0x48080000, + .pa_end = 0x48080000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_elm_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_elm_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = { + { + .pa_start = 0x48300000, + .pa_end = 0x48300000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48300200, + .pa_end = 0x48300200 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ehrpwm0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ehrpwm0_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = { + { + .pa_start = 0x48302000, + .pa_end = 0x48302000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48302200, + .pa_end = 0x48302200 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ehrpwm1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ehrpwm1_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = { + { + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48304200, + .pa_end = 0x48304200 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ehrpwm2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ehrpwm2_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = { + { + .pa_start = 0x48300000, + .pa_end = 0x48300000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48300100, + .pa_end = 0x48300100 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ecap0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ecap0_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = { + { + .pa_start = 0x48302000, + .pa_end = 0x48302000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48302100, + .pa_end = 0x48302100 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ecap1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ecap1_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = { + { + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48304100, + .pa_end = 0x48304100 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ecap2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ecap2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3s cfg -> gpmc */ +static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { + { + .pa_start = 0x50000000, + .pa_end = 0x50000000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_gpmc_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_gpmc_addr_space, + .user = OCP_USER_MPU, +}; + +/* i2c2 */ +static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = { + { + .pa_start = 0x4802A000, + .pa_end = 0x4802A000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_i2c2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_i2c2_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = { + { + .pa_start = 0x4819C000, + .pa_end = 0x4819C000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_i2c3_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_i2c3_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { + { + .pa_start = 0x4830E000, + .pa_end = 0x4830E000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_lcdc_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_lcdc_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { + { + .pa_start = 0x480C8000, + .pa_end = 0x480C8000 + (SZ_4K - 1), + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4 ls -> mailbox */ +static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mailbox_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mailbox_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> spinlock */ +static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = { + { + .pa_start = 0x480Ca000, + .pa_end = 0x480Ca000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_spinlock_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_spinlock_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcasp0 */ +static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { + { + .pa_start = 0x48038000, + .pa_end = 0x48038000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mcasp0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcasp0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 s -> mcasp0 data */ +static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = { + { + .pa_start = 0x46000000, + .pa_end = 0x46000000 + SZ_4M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_mcasp0_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_mcasp0_data_addr_space, + .user = OCP_USER_SDMA, +}; + +/* l4 ls -> mcasp1 */ +static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { + { + .pa_start = 0x4803C000, + .pa_end = 0x4803C000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mcasp1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcasp1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 s -> mcasp1 data */ +static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = { + { + .pa_start = 0x46400000, + .pa_end = 0x46400000 + SZ_4M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_mcasp1_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_mcasp1_data_addr_space, + .user = OCP_USER_SDMA, +}; + +/* l4 ls -> mmc0 */ +static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { + { + .pa_start = 0x48060100, + .pa_end = 0x48060100 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mmc0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mmc0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mmc1 */ +static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { + { + .pa_start = 0x481d8100, + .pa_end = 0x481d8100 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mmc1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mmc1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 s -> mmc2 */ +static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { + { + .pa_start = 0x47810100, + .pa_end = 0x47810100 + SZ_64K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_mmc2_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_mmc2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcspi0 */ +static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = { + { + .pa_start = 0x48030000, + .pa_end = 0x48030000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_spi0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcspi0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcspi1 */ +static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = { + { + .pa_start = 0x481A0000, + .pa_end = 0x481A0000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_spi1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcspi1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> timer1 */ +static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = { + { + .pa_start = 0x44E31000, + .pa_end = 0x44E31000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_timer1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_timer1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer2 */ +static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = { + { + .pa_start = 0x48040000, + .pa_end = 0x48040000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer3 */ +static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = { + { + .pa_start = 0x48042000, + .pa_end = 0x48042000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer3_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer3_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer4 */ +static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = { + { + .pa_start = 0x48044000, + .pa_end = 0x48044000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer4_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer4_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer5 */ +static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = { + { + .pa_start = 0x48046000, + .pa_end = 0x48046000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer5_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer5_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer6 */ +static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = { + { + .pa_start = 0x48048000, + .pa_end = 0x48048000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer6_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer6_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer7 */ +static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = { + { + .pa_start = 0x4804A000, + .pa_end = 0x4804A000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer7_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer7_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc */ +static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = { + { + .pa_start = 0x49000000, + .pa_end = 0x49000000 + SZ_32K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tpcc_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tpcc_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc0 */ +static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { + { + .pa_start = 0x49800000, + .pa_end = 0x49800000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tptc0_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tptc0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc1 */ +static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { + { + .pa_start = 0x49900000, + .pa_end = 0x49900000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tptc1_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tptc1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc2 */ +static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { + { + .pa_start = 0x49a00000, + .pa_end = 0x49a00000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tptc2_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tptc2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> uart1 */ +static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = { + { + .pa_start = 0x44E09000, + .pa_end = 0x44E09000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_uart1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_uart1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart2 */ +static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = { + { + .pa_start = 0x48022000, + .pa_end = 0x48022000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart3 */ +static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = { + { + .pa_start = 0x48024000, + .pa_end = 0x48024000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart3_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart3_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart4 */ +static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = { + { + .pa_start = 0x481A6000, + .pa_end = 0x481A6000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart4_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart4_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart5 */ +static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = { + { + .pa_start = 0x481A8000, + .pa_end = 0x481A8000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart5_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart5_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart6 */ +static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = { + { + .pa_start = 0x481aa000, + .pa_end = 0x481aa000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart6_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart6_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> wd_timer1 */ +static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = { + { + .pa_start = 0x44e35000, + .pa_end = 0x44e35000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_wd_timer1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_wd_timer1_addrs, + .user = OCP_USER_MPU, +}; + +/* usbss */ +/* l3 s -> USBSS interface */ +static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = { + { + .name = "usbss", + .pa_start = 0x47400000, + .pa_end = 0x47400000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { + .name = "musb0", + .pa_start = 0x47401000, + .pa_end = 0x47401000 + SZ_2K - 1, + .flags = ADDR_TYPE_RT + }, + { + .name = "musb1", + .pa_start = 0x47401800, + .pa_end = 0x47401800 + SZ_2K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_usbss_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_usbss_addr_space, + .user = OCP_USER_MPU, + .flags = OCPIF_SWSUP_IDLE, +}; + +static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { + &am33xx_l4_fw__emif_fw, + &am33xx_l3_main__emif, + &am33xx_mpu__l3_main, + &am33xx_mpu__prcm, + &am33xx_l3_s__l4_ls, + &am33xx_l3_s__l4_wkup, + &am33xx_l3_s__l4_fw, + &am33xx_l3_main__l4_hs, + &am33xx_l3_main__l3_s, + &am33xx_l3_main__l3_instr, + &am33xx_l3_main__gfx, + &am33xx_l3_s__l3_main, + &am33xx_pruss__l3_main, + &am33xx_wkup_m3__l4_wkup, + &am33xx_gfx__l3_main, + &am33xx_l4_wkup__wkup_m3, + &am33xx_l4_wkup__control, + &am33xx_l4_wkup__smartreflex0, + &am33xx_l4_wkup__smartreflex1, + &am33xx_l4_wkup__uart1, + &am33xx_l4_wkup__timer1, + &am33xx_l4_wkup__rtc, + &am33xx_l4_wkup__i2c1, + &am33xx_l4_wkup__gpio0, + &am33xx_l4_wkup__adc_tsc, + &am33xx_l4_wkup__wd_timer1, + &am33xx_l4_hs__pruss, + &am33xx_l4_per__dcan0, + &am33xx_l4_per__dcan1, + &am33xx_l4_per__gpio1, + &am33xx_l4_per__gpio2, + &am33xx_l4_per__gpio3, + &am33xx_l4_per__i2c2, + &am33xx_l4_per__i2c3, + &am33xx_l4_per__mailbox, + &am33xx_l4_ls__mcasp0, + &am33xx_l3_s__mcasp0_data, + &am33xx_l4_ls__mcasp1, + &am33xx_l3_s__mcasp1_data, + &am33xx_l4_ls__mmc0, + &am33xx_l4_ls__mmc1, + &am33xx_l3_s__mmc2, + &am33xx_l4_ls__timer2, + &am33xx_l4_ls__timer3, + &am33xx_l4_ls__timer4, + &am33xx_l4_ls__timer5, + &am33xx_l4_ls__timer6, + &am33xx_l4_ls__timer7, + &am33xx_l3_main__tpcc, + &am33xx_l4_ls__uart2, + &am33xx_l4_ls__uart3, + &am33xx_l4_ls__uart4, + &am33xx_l4_ls__uart5, + &am33xx_l4_ls__uart6, + &am33xx_l4_ls__spinlock, + &am33xx_l4_ls__elm, + &am33xx_l4_ls__ehrpwm0, + &am33xx_l4_ls__ehrpwm1, + &am33xx_l4_ls__ehrpwm2, + &am33xx_l4_ls__ecap0, + &am33xx_l4_ls__ecap1, + &am33xx_l4_ls__ecap2, + &am33xx_l3_s__gpmc, + &am33xx_l3_main__lcdc, + &am33xx_l4_ls__mcspi0, + &am33xx_l4_ls__mcspi1, + &am33xx_l3_main__tptc0, + &am33xx_l3_main__tptc1, + &am33xx_l3_main__tptc2, + &am33xx_l3_s__usbss, + &am33xx_l4_hs__cpgmac0, + NULL, +}; + +int __init am33xx_hwmod_init(void) +{ + omap_hwmod_init(); + return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); +} diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index ce7e6068768..94b38af1705 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -15,26 +15,26 @@ * XXX these should be marked initdata for multi-OMAP kernels */ #include <linux/power/smartreflex.h> +#include <linux/platform_data/gpio-omap.h> #include <plat/omap_hwmod.h> -#include <mach/irqs.h> -#include <plat/cpu.h> #include <plat/dma.h> #include <plat/serial.h> -#include <plat/l3_3xxx.h> -#include <plat/l4_3xxx.h> +#include "l3_3xxx.h" +#include "l4_3xxx.h" #include <plat/i2c.h> -#include <plat/gpio.h> #include <plat/mmc.h> -#include <plat/mcbsp.h> -#include <plat/mcspi.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <plat/dmtimer.h> +#include "am35xx.h" + +#include "soc.h" #include "omap_hwmod_common_data.h" #include "prm-regbits-34xx.h" #include "cm-regbits-34xx.h" #include "wd_timer.h" -#include <mach/am35xx.h> /* * OMAP3xxx hardware module integration data @@ -51,9 +51,9 @@ /* L3 */ static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { - { .irq = INT_34XX_L3_DBG_IRQ }, - { .irq = INT_34XX_L3_APP_IRQ }, - { .irq = -1 } + { .irq = 9 + OMAP_INTC_START, }, + { .irq = 10 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_l3_main_hwmod = { @@ -364,8 +364,8 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { /* timer12 */ static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { - { .irq = 95, }, - { .irq = -1 } + { .irq = 95 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_timer12_hwmod = { @@ -499,8 +499,8 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { /* UART4 */ static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { - { .irq = INT_36XX_UART4_IRQ, }, - { .irq = -1 } + { .irq = 80 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { @@ -527,8 +527,8 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { }; static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { - { .irq = INT_35XX_UART4_IRQ, }, - { .irq = -1 } + { .irq = 84 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { @@ -683,8 +683,8 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { }; static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { - { .irq = 25 }, - { .irq = -1 } + { .irq = 25 + OMAP_INTC_START, }, + { .irq = -1 }, }; /* dss_dsi1 */ @@ -813,8 +813,8 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = { }; static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { - { .irq = INT_34XX_I2C3_IRQ, }, - { .irq = -1 } + { .irq = 61 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { @@ -972,8 +972,8 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { /* gpio5 */ static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { - { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ - { .irq = -1 } + { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ + { .irq = -1 }, }; static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { @@ -1002,8 +1002,8 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { /* gpio6 */ static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { - { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ - { .irq = -1 } + { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ + { .irq = -1 }, }; static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { @@ -1107,10 +1107,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { /* mcbsp1 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { - { .name = "common", .irq = 16 }, - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .irq = -1 } + { .name = "common", .irq = 16 + OMAP_INTC_START, }, + { .name = "tx", .irq = 59 + OMAP_INTC_START, }, + { .name = "rx", .irq = 60 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { @@ -1134,10 +1134,10 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { /* mcbsp2 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { - { .name = "common", .irq = 17 }, - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .irq = -1 } + { .name = "common", .irq = 17 + OMAP_INTC_START, }, + { .name = "tx", .irq = 62 + OMAP_INTC_START, }, + { .name = "rx", .irq = 63 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { @@ -1166,10 +1166,10 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { /* mcbsp3 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { - { .name = "common", .irq = 22 }, - { .name = "tx", .irq = 89 }, - { .name = "rx", .irq = 90 }, - { .irq = -1 } + { .name = "common", .irq = 22 + OMAP_INTC_START, }, + { .name = "tx", .irq = 89 + OMAP_INTC_START, }, + { .name = "rx", .irq = 90 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { @@ -1198,10 +1198,10 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { /* mcbsp4 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { - { .name = "common", .irq = 23 }, - { .name = "tx", .irq = 54 }, - { .name = "rx", .irq = 55 }, - { .irq = -1 } + { .name = "common", .irq = 23 + OMAP_INTC_START, }, + { .name = "tx", .irq = 54 + OMAP_INTC_START, }, + { .name = "rx", .irq = 55 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { @@ -1231,10 +1231,10 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { /* mcbsp5 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { - { .name = "common", .irq = 27 }, - { .name = "tx", .irq = 81 }, - { .name = "rx", .irq = 82 }, - { .irq = -1 } + { .name = "common", .irq = 27 + OMAP_INTC_START, }, + { .name = "tx", .irq = 81 + OMAP_INTC_START, }, + { .name = "rx", .irq = 82 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { @@ -1276,8 +1276,8 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { /* mcbsp2_sidetone */ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { - { .name = "irq", .irq = 4 }, - { .irq = -1 } + { .name = "irq", .irq = 4 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { @@ -1298,8 +1298,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { /* mcbsp3_sidetone */ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { - { .name = "irq", .irq = 5 }, - { .irq = -1 } + { .name = "irq", .irq = 5 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { @@ -1361,8 +1361,8 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = { }; static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { - { .irq = 18 }, - { .irq = -1 } + { .irq = 18 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap34xx_sr1_hwmod = { @@ -1406,8 +1406,8 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = { }; static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { - { .irq = 19 }, - { .irq = -1 } + { .irq = 19 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap34xx_sr2_hwmod = { @@ -1467,8 +1467,8 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { }; static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { - { .irq = 26 }, - { .irq = -1 } + { .irq = 26 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_mailbox_hwmod = { @@ -1558,8 +1558,8 @@ static struct omap_hwmod omap34xx_mcspi2 = { /* mcspi3 */ static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { - { .name = "irq", .irq = 91 }, /* 91 */ - { .irq = -1 } + { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { @@ -1594,8 +1594,8 @@ static struct omap_hwmod omap34xx_mcspi3 = { /* mcspi4 */ static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { - { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ - { .irq = -1 } + { .name = "irq", .irq = 48 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { @@ -1647,9 +1647,9 @@ static struct omap_hwmod_class usbotg_class = { /* usb_otg_hs */ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { - { .name = "mc", .irq = 92 }, - { .name = "dma", .irq = 93 }, - { .irq = -1 } + { .name = "mc", .irq = 92 + OMAP_INTC_START, }, + { .name = "dma", .irq = 93 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { @@ -1679,8 +1679,8 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { /* usb_otg_hs */ static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { - { .name = "mc", .irq = 71 }, - { .irq = -1 } + { .name = "mc", .irq = 71 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_class am35xx_usbotg_class = { @@ -1715,8 +1715,8 @@ static struct omap_hwmod_class omap34xx_mmc_class = { /* MMC/SD/SDIO1 */ static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { - { .irq = 83, }, - { .irq = -1 } + { .irq = 83 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { @@ -1782,8 +1782,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { /* MMC/SD/SDIO2 */ static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { - { .irq = INT_24XX_MMC2_IRQ, }, - { .irq = -1 } + { .irq = 86 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { @@ -1843,8 +1843,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { /* MMC/SD/SDIO3 */ static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { - { .irq = 94, }, - { .irq = -1 } + { .irq = 94 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { @@ -1902,9 +1902,9 @@ static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { }; static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { - { .name = "ohci-irq", .irq = 76 }, - { .name = "ehci-irq", .irq = 77 }, - { .irq = -1 } + { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, + { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { @@ -1996,8 +1996,8 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { }; static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { - { .name = "tll-irq", .irq = 78 }, - { .irq = -1 } + { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { @@ -3223,11 +3223,11 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { }; static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { - { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ }, - { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ }, - { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ }, - { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ }, - { .irq = -1 } + { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, }, + { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, }, + { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START }, + { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START }, + { .irq = -1 }, }; static struct omap_hwmod_class am35xx_emac_class = { diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index afb60917a94..c7dcb606cd0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -19,15 +19,14 @@ */ #include <linux/io.h> +#include <linux/platform_data/gpio-omap.h> #include <linux/power/smartreflex.h> #include <plat/omap_hwmod.h> -#include <plat/cpu.h> #include <plat/i2c.h> -#include <plat/gpio.h> #include <plat/dma.h> -#include <plat/mcspi.h> -#include <plat/mcbsp.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> #include <plat/mmc.h> #include <plat/dmtimer.h> #include <plat/common.h> @@ -5890,6 +5889,12 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { .pa_end = 0x4a0ab003, .flags = ADDR_TYPE_RT }, + { + /* XXX: Remove this once control module driver is in place */ + .pa_start = 0x4a00233c, + .pa_end = 0x4a00233f, + .flags = ADDR_TYPE_RT + }, { } }; diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index e7e8eeae95e..dddb677fed6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -16,6 +16,7 @@ #include <plat/omap_hwmod.h> +#include "common.h" #include "display.h" /* Common address space across OMAP2xxx */ diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c deleted file mode 100644 index d15225ff5c4..00000000000 --- a/arch/arm/mach-omap2/omap_l3_noc.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * OMAP4XXX L3 Interconnect error handling driver - * - * Copyright (C) 2011 Texas Corporation - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * Sricharan <r.sricharan@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 - * USA - */ -#include <linux/module.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/slab.h> - -#include "omap_l3_noc.h" - -/* - * Interrupt Handler for L3 error detection. - * 1) Identify the L3 clockdomain partition to which the error belongs to. - * 2) Identify the slave where the error information is logged - * 3) Print the logged information. - * 4) Add dump stack to provide kernel trace. - * - * Two Types of errors : - * 1) Custom errors in L3 : - * Target like DMM/FW/EMIF generates SRESP=ERR error - * 2) Standard L3 error: - * - Unsupported CMD. - * L3 tries to access target while it is idle - * - OCP disconnect. - * - Address hole error: - * If DSS/ISS/FDIF/USBHOSTFS access a target where they - * do not have connectivity, the error is logged in - * their default target which is DMM2. - * - * On High Secure devices, firewall errors are possible and those - * can be trapped as well. But the trapping is implemented as part - * secure software and hence need not be implemented here. - */ -static irqreturn_t l3_interrupt_handler(int irq, void *_l3) -{ - - struct omap4_l3 *l3 = _l3; - int inttype, i, k; - int err_src = 0; - u32 std_err_main, err_reg, clear, masterid; - void __iomem *base, *l3_targ_base; - char *target_name, *master_name = "UN IDENTIFIED"; - - /* Get the Type of interrupt */ - inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; - - for (i = 0; i < L3_MODULES; i++) { - /* - * Read the regerr register of the clock domain - * to determine the source - */ - base = l3->l3_base[i]; - err_reg = __raw_readl(base + l3_flagmux[i] + - + L3_FLAGMUX_REGERR0 + (inttype << 3)); - - /* Get the corresponding error and analyse */ - if (err_reg) { - /* Identify the source from control status register */ - err_src = __ffs(err_reg); - - /* Read the stderrlog_main_source from clk domain */ - l3_targ_base = base + *(l3_targ[i] + err_src); - std_err_main = __raw_readl(l3_targ_base + - L3_TARG_STDERRLOG_MAIN); - masterid = __raw_readl(l3_targ_base + - L3_TARG_STDERRLOG_MSTADDR); - - switch (std_err_main & CUSTOM_ERROR) { - case STANDARD_ERROR: - target_name = - l3_targ_inst_name[i][err_src]; - WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n", - target_name, - __raw_readl(l3_targ_base + - L3_TARG_STDERRLOG_SLVOFSLSB)); - /* clear the std error log*/ - clear = std_err_main | CLEAR_STDERR_LOG; - writel(clear, l3_targ_base + - L3_TARG_STDERRLOG_MAIN); - break; - - case CUSTOM_ERROR: - target_name = - l3_targ_inst_name[i][err_src]; - for (k = 0; k < NUM_OF_L3_MASTERS; k++) { - if (masterid == l3_masters[k].id) - master_name = - l3_masters[k].name; - } - WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n", - master_name, target_name); - /* clear the std error log*/ - clear = std_err_main | CLEAR_STDERR_LOG; - writel(clear, l3_targ_base + - L3_TARG_STDERRLOG_MAIN); - break; - - default: - /* Nothing to be handled here as of now */ - break; - } - /* Error found so break the for loop */ - break; - } - } - return IRQ_HANDLED; -} - -static int __devinit omap4_l3_probe(struct platform_device *pdev) -{ - static struct omap4_l3 *l3; - struct resource *res; - int ret; - - l3 = kzalloc(sizeof(*l3), GFP_KERNEL); - if (!l3) - return -ENOMEM; - - platform_set_drvdata(pdev, l3); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "couldn't find resource 0\n"); - ret = -ENODEV; - goto err0; - } - - l3->l3_base[0] = ioremap(res->start, resource_size(res)); - if (!l3->l3_base[0]) { - dev_err(&pdev->dev, "ioremap failed\n"); - ret = -ENOMEM; - goto err0; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!res) { - dev_err(&pdev->dev, "couldn't find resource 1\n"); - ret = -ENODEV; - goto err1; - } - - l3->l3_base[1] = ioremap(res->start, resource_size(res)); - if (!l3->l3_base[1]) { - dev_err(&pdev->dev, "ioremap failed\n"); - ret = -ENOMEM; - goto err1; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 2); - if (!res) { - dev_err(&pdev->dev, "couldn't find resource 2\n"); - ret = -ENODEV; - goto err2; - } - - l3->l3_base[2] = ioremap(res->start, resource_size(res)); - if (!l3->l3_base[2]) { - dev_err(&pdev->dev, "ioremap failed\n"); - ret = -ENOMEM; - goto err2; - } - - /* - * Setup interrupt Handlers - */ - l3->debug_irq = platform_get_irq(pdev, 0); - ret = request_irq(l3->debug_irq, - l3_interrupt_handler, - IRQF_DISABLED, "l3-dbg-irq", l3); - if (ret) { - pr_crit("L3: request_irq failed to register for 0x%x\n", - OMAP44XX_IRQ_L3_DBG); - goto err3; - } - - l3->app_irq = platform_get_irq(pdev, 1); - ret = request_irq(l3->app_irq, - l3_interrupt_handler, - IRQF_DISABLED, "l3-app-irq", l3); - if (ret) { - pr_crit("L3: request_irq failed to register for 0x%x\n", - OMAP44XX_IRQ_L3_APP); - goto err4; - } - - return 0; - -err4: - free_irq(l3->debug_irq, l3); -err3: - iounmap(l3->l3_base[2]); -err2: - iounmap(l3->l3_base[1]); -err1: - iounmap(l3->l3_base[0]); -err0: - kfree(l3); - return ret; -} - -static int __devexit omap4_l3_remove(struct platform_device *pdev) -{ - struct omap4_l3 *l3 = platform_get_drvdata(pdev); - - free_irq(l3->app_irq, l3); - free_irq(l3->debug_irq, l3); - iounmap(l3->l3_base[0]); - iounmap(l3->l3_base[1]); - iounmap(l3->l3_base[2]); - kfree(l3); - - return 0; -} - -#if defined(CONFIG_OF) -static const struct of_device_id l3_noc_match[] = { - {.compatible = "ti,omap4-l3-noc", }, - {}, -}; -MODULE_DEVICE_TABLE(of, l3_noc_match); -#else -#define l3_noc_match NULL -#endif - -static struct platform_driver omap4_l3_driver = { - .probe = omap4_l3_probe, - .remove = __devexit_p(omap4_l3_remove), - .driver = { - .name = "omap_l3_noc", - .owner = THIS_MODULE, - .of_match_table = l3_noc_match, - }, -}; - -static int __init omap4_l3_init(void) -{ - return platform_driver_register(&omap4_l3_driver); -} -postcore_initcall_sync(omap4_l3_init); - -static void __exit omap4_l3_exit(void) -{ - platform_driver_unregister(&omap4_l3_driver); -} -module_exit(omap4_l3_exit); diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h deleted file mode 100644 index a6ce34dc481..00000000000 --- a/arch/arm/mach-omap2/omap_l3_noc.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * OMAP4XXX L3 Interconnect error handling driver header - * - * Copyright (C) 2011 Texas Corporation - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * sricharan <r.sricharan@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 - * USA - */ -#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H -#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H - -#define L3_MODULES 3 -#define CLEAR_STDERR_LOG (1 << 31) -#define CUSTOM_ERROR 0x2 -#define STANDARD_ERROR 0x0 -#define INBAND_ERROR 0x0 -#define L3_APPLICATION_ERROR 0x0 -#define L3_DEBUG_ERROR 0x1 - -/* L3 TARG register offsets */ -#define L3_TARG_STDERRLOG_MAIN 0x48 -#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c -#define L3_TARG_STDERRLOG_MSTADDR 0x68 -#define L3_FLAGMUX_REGERR0 0xc - -#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0])) - -static u32 l3_flagmux[L3_MODULES] = { - 0x500, - 0x1000, - 0X0200 -}; - -/* L3 Target standard Error register offsets */ -static u32 l3_targ_inst_clk1[] = { - 0x100, /* DMM1 */ - 0x200, /* DMM2 */ - 0x300, /* ABE */ - 0x400, /* L4CFG */ - 0x600, /* CLK2 PWR DISC */ - 0x0, /* Host CLK1 */ - 0x900 /* L4 Wakeup */ -}; - -static u32 l3_targ_inst_clk2[] = { - 0x500, /* CORTEX M3 */ - 0x300, /* DSS */ - 0x100, /* GPMC */ - 0x400, /* ISS */ - 0x700, /* IVAHD */ - 0xD00, /* missing in TRM corresponds to AES1*/ - 0x900, /* L4 PER0*/ - 0x200, /* OCMRAM */ - 0x100, /* missing in TRM corresponds to GPMC sERROR*/ - 0x600, /* SGX */ - 0x800, /* SL2 */ - 0x1600, /* C2C */ - 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/ - 0xF00, /* missing in TRM corrsponds to SHA1*/ - 0xE00, /* missing in TRM corresponds to AES2*/ - 0xC00, /* L4 PER3 */ - 0xA00, /* L4 PER1*/ - 0xB00, /* L4 PER2*/ - 0x0, /* HOST CLK2 */ - 0x1800, /* CAL */ - 0x1700 /* LLI */ -}; - -static u32 l3_targ_inst_clk3[] = { - 0x0100 /* EMUSS */, - 0x0300, /* DEBUGSS_CT_TBR */ - 0x0 /* HOST CLK3 */ -}; - -static struct l3_masters_data { - u32 id; - char name[10]; -} l3_masters[] = { - { 0x0 , "MPU"}, - { 0x10, "CS_ADP"}, - { 0x14, "xxx"}, - { 0x20, "DSP"}, - { 0x30, "IVAHD"}, - { 0x40, "ISS"}, - { 0x44, "DucatiM3"}, - { 0x48, "FaceDetect"}, - { 0x50, "SDMA_Rd"}, - { 0x54, "SDMA_Wr"}, - { 0x58, "xxx"}, - { 0x5C, "xxx"}, - { 0x60, "SGX"}, - { 0x70, "DSS"}, - { 0x80, "C2C"}, - { 0x88, "xxx"}, - { 0x8C, "xxx"}, - { 0x90, "HSI"}, - { 0xA0, "MMC1"}, - { 0xA4, "MMC2"}, - { 0xA8, "MMC6"}, - { 0xB0, "UNIPRO1"}, - { 0xC0, "USBHOSTHS"}, - { 0xC4, "USBOTGHS"}, - { 0xC8, "USBHOSTFS"} -}; - -static char *l3_targ_inst_name[L3_MODULES][21] = { - { - "DMM1", - "DMM2", - "ABE", - "L4CFG", - "CLK2 PWR DISC", - "HOST CLK1", - "L4 WAKEUP" - }, - { - "CORTEX M3" , - "DSS ", - "GPMC ", - "ISS ", - "IVAHD ", - "AES1", - "L4 PER0", - "OCMRAM ", - "GPMC sERROR", - "SGX ", - "SL2 ", - "C2C ", - "PWR DISC CLK1", - "SHA1", - "AES2", - "L4 PER3", - "L4 PER1", - "L4 PER2", - "HOST CLK2", - "CAL", - "LLI" - }, - { - "EMUSS", - "DEBUG SOURCE", - "HOST CLK3" - }, -}; - -static u32 *l3_targ[L3_MODULES] = { - l3_targ_inst_clk1, - l3_targ_inst_clk2, - l3_targ_inst_clk3, -}; - -struct omap4_l3 { - struct device *dev; - struct clk *ick; - - /* memory base */ - void __iomem *l3_base[L3_MODULES]; - - int debug_irq; - int app_irq; -}; -#endif diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c deleted file mode 100644 index acc216491b8..00000000000 --- a/arch/arm/mach-omap2/omap_l3_smx.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * OMAP3XXX L3 Interconnect Driver - * - * Copyright (C) 2011 Texas Corporation - * Felipe Balbi <balbi@ti.com> - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * Sricharan <r.sricharan@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 - * USA - */ - -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include "omap_l3_smx.h" - -static inline u64 omap3_l3_readll(void __iomem *base, u16 reg) -{ - return __raw_readll(base + reg); -} - -static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value) -{ - __raw_writell(value, base + reg); -} - -static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error) -{ - return (error & 0x0f000000) >> L3_ERROR_LOG_CODE; -} - -static inline u32 omap3_l3_decode_addr(u64 error_addr) -{ - return error_addr & 0xffffffff; -} - -static inline unsigned omap3_l3_decode_cmd(u64 error) -{ - return (error & 0x07) >> L3_ERROR_LOG_CMD; -} - -static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error) -{ - return (error & 0xff00) >> L3_ERROR_LOG_INITID; -} - -static inline unsigned omap3_l3_decode_req_info(u64 error) -{ - return (error >> 32) & 0xffff; -} - -static char *omap3_l3_code_string(u8 code) -{ - switch (code) { - case OMAP_L3_CODE_NOERROR: - return "No Error"; - case OMAP_L3_CODE_UNSUP_CMD: - return "Unsupported Command"; - case OMAP_L3_CODE_ADDR_HOLE: - return "Address Hole"; - case OMAP_L3_CODE_PROTECT_VIOLATION: - return "Protection Violation"; - case OMAP_L3_CODE_IN_BAND_ERR: - return "In-band Error"; - case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT: - return "Request Timeout Not Accepted"; - case OMAP_L3_CODE_REQ_TOUT_NO_RESP: - return "Request Timeout, no response"; - default: - return "UNKNOWN error"; - } -} - -static char *omap3_l3_initiator_string(u8 initid) -{ - switch (initid) { - case OMAP_L3_LCD: - return "LCD"; - case OMAP_L3_SAD2D: - return "SAD2D"; - case OMAP_L3_IA_MPU_SS_1: - case OMAP_L3_IA_MPU_SS_2: - case OMAP_L3_IA_MPU_SS_3: - case OMAP_L3_IA_MPU_SS_4: - case OMAP_L3_IA_MPU_SS_5: - return "MPU"; - case OMAP_L3_IA_IVA_SS_1: - case OMAP_L3_IA_IVA_SS_2: - case OMAP_L3_IA_IVA_SS_3: - return "IVA_SS"; - case OMAP_L3_IA_IVA_SS_DMA_1: - case OMAP_L3_IA_IVA_SS_DMA_2: - case OMAP_L3_IA_IVA_SS_DMA_3: - case OMAP_L3_IA_IVA_SS_DMA_4: - case OMAP_L3_IA_IVA_SS_DMA_5: - case OMAP_L3_IA_IVA_SS_DMA_6: - return "IVA_SS_DMA"; - case OMAP_L3_IA_SGX: - return "SGX"; - case OMAP_L3_IA_CAM_1: - case OMAP_L3_IA_CAM_2: - case OMAP_L3_IA_CAM_3: - return "CAM"; - case OMAP_L3_IA_DAP: - return "DAP"; - case OMAP_L3_SDMA_WR_1: - case OMAP_L3_SDMA_WR_2: - return "SDMA_WR"; - case OMAP_L3_SDMA_RD_1: - case OMAP_L3_SDMA_RD_2: - case OMAP_L3_SDMA_RD_3: - case OMAP_L3_SDMA_RD_4: - return "SDMA_RD"; - case OMAP_L3_USBOTG: - return "USB_OTG"; - case OMAP_L3_USBHOST: - return "USB_HOST"; - default: - return "UNKNOWN Initiator"; - } -} - -/* - * omap3_l3_block_irq - handles a register block's irq - * @l3: struct omap3_l3 * - * @base: register block base address - * @error: L3_ERROR_LOG register of our block - * - * Called in hard-irq context. Caller should take care of locking - * - * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error - * Analysis Sequence, we are following that sequence here, please - * refer to that Figure for more information on the subject. - */ -static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3, - u64 error, int error_addr) -{ - u8 code = omap3_l3_decode_error_code(error); - u8 initid = omap3_l3_decode_initid(error); - u8 multi = error & L3_ERROR_LOG_MULTI; - u32 address = omap3_l3_decode_addr(error_addr); - - pr_err("%s seen by %s %s at address %x\n", - omap3_l3_code_string(code), - omap3_l3_initiator_string(initid), - multi ? "Multiple Errors" : "", address); - WARN_ON(1); - - return IRQ_HANDLED; -} - -static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) -{ - struct omap3_l3 *l3 = _l3; - u64 status, clear; - u64 error; - u64 error_addr; - u64 err_source = 0; - void __iomem *base; - int int_type; - irqreturn_t ret = IRQ_NONE; - - int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; - if (!int_type) { - status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0); - /* - * if we have a timeout error, there's nothing we can - * do besides rebooting the board. So let's BUG on any - * of such errors and handle the others. timeout error - * is severe and not expected to occur. - */ - BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK); - } else { - status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1); - /* No timeout error for debug sources */ - } - - /* identify the error source */ - err_source = __ffs(status); - - base = l3->rt + omap3_l3_bases[int_type][err_source]; - error = omap3_l3_readll(base, L3_ERROR_LOG); - if (error) { - error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR); - ret |= omap3_l3_block_irq(l3, error, error_addr); - } - - /* Clear the status register */ - clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) | - L3_AGENT_STATUS_CLEAR_TA; - omap3_l3_writell(base, L3_AGENT_STATUS, clear); - - /* clear the error log register */ - omap3_l3_writell(base, L3_ERROR_LOG, error); - - return ret; -} - -static int __init omap3_l3_probe(struct platform_device *pdev) -{ - struct omap3_l3 *l3; - struct resource *res; - int ret; - - l3 = kzalloc(sizeof(*l3), GFP_KERNEL); - if (!l3) - return -ENOMEM; - - platform_set_drvdata(pdev, l3); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "couldn't find resource\n"); - ret = -ENODEV; - goto err0; - } - l3->rt = ioremap(res->start, resource_size(res)); - if (!l3->rt) { - dev_err(&pdev->dev, "ioremap failed\n"); - ret = -ENOMEM; - goto err0; - } - - l3->debug_irq = platform_get_irq(pdev, 0); - ret = request_irq(l3->debug_irq, omap3_l3_app_irq, - IRQF_DISABLED | IRQF_TRIGGER_RISING, - "l3-debug-irq", l3); - if (ret) { - dev_err(&pdev->dev, "couldn't request debug irq\n"); - goto err1; - } - - l3->app_irq = platform_get_irq(pdev, 1); - ret = request_irq(l3->app_irq, omap3_l3_app_irq, - IRQF_DISABLED | IRQF_TRIGGER_RISING, - "l3-app-irq", l3); - if (ret) { - dev_err(&pdev->dev, "couldn't request app irq\n"); - goto err2; - } - - return 0; - -err2: - free_irq(l3->debug_irq, l3); -err1: - iounmap(l3->rt); -err0: - kfree(l3); - return ret; -} - -static int __exit omap3_l3_remove(struct platform_device *pdev) -{ - struct omap3_l3 *l3 = platform_get_drvdata(pdev); - - free_irq(l3->app_irq, l3); - free_irq(l3->debug_irq, l3); - iounmap(l3->rt); - kfree(l3); - - return 0; -} - -static struct platform_driver omap3_l3_driver = { - .remove = __exit_p(omap3_l3_remove), - .driver = { - .name = "omap_l3_smx", - }, -}; - -static int __init omap3_l3_init(void) -{ - return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe); -} -postcore_initcall_sync(omap3_l3_init); - -static void __exit omap3_l3_exit(void) -{ - platform_driver_unregister(&omap3_l3_driver); -} -module_exit(omap3_l3_exit); diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h deleted file mode 100644 index 4f3cebca417..00000000000 --- a/arch/arm/mach-omap2/omap_l3_smx.h +++ /dev/null @@ -1,338 +0,0 @@ -/* - * OMAP3XXX L3 Interconnect Driver header - * - * Copyright (C) 2011 Texas Corporation - * Felipe Balbi <balbi@ti.com> - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * sricharan <r.sricharan@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 - * USA - */ -#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H -#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H - -/* Register definitions. All 64-bit wide */ -#define L3_COMPONENT 0x000 -#define L3_CORE 0x018 -#define L3_AGENT_CONTROL 0x020 -#define L3_AGENT_STATUS 0x028 -#define L3_ERROR_LOG 0x058 - -#define L3_ERROR_LOG_MULTI (1 << 31) -#define L3_ERROR_LOG_SECONDARY (1 << 30) - -#define L3_ERROR_LOG_ADDR 0x060 - -/* Register definitions for Sideband Interconnect */ -#define L3_SI_CONTROL 0x020 -#define L3_SI_FLAG_STATUS_0 0x510 - -static const u64 shift = 1; - -#define L3_STATUS_0_MPUIA_BRST (shift << 0) -#define L3_STATUS_0_MPUIA_RSP (shift << 1) -#define L3_STATUS_0_MPUIA_INBAND (shift << 2) -#define L3_STATUS_0_IVAIA_BRST (shift << 6) -#define L3_STATUS_0_IVAIA_RSP (shift << 7) -#define L3_STATUS_0_IVAIA_INBAND (shift << 8) -#define L3_STATUS_0_SGXIA_BRST (shift << 9) -#define L3_STATUS_0_SGXIA_RSP (shift << 10) -#define L3_STATUS_0_SGXIA_MERROR (shift << 11) -#define L3_STATUS_0_CAMIA_BRST (shift << 12) -#define L3_STATUS_0_CAMIA_RSP (shift << 13) -#define L3_STATUS_0_CAMIA_INBAND (shift << 14) -#define L3_STATUS_0_DISPIA_BRST (shift << 15) -#define L3_STATUS_0_DISPIA_RSP (shift << 16) -#define L3_STATUS_0_DMARDIA_BRST (shift << 18) -#define L3_STATUS_0_DMARDIA_RSP (shift << 19) -#define L3_STATUS_0_DMAWRIA_BRST (shift << 21) -#define L3_STATUS_0_DMAWRIA_RSP (shift << 22) -#define L3_STATUS_0_USBOTGIA_BRST (shift << 24) -#define L3_STATUS_0_USBOTGIA_RSP (shift << 25) -#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26) -#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27) -#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28) -#define L3_STATUS_0_SMSTA_REQ (shift << 48) -#define L3_STATUS_0_GPMCTA_REQ (shift << 49) -#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50) -#define L3_STATUS_0_OCMROMTA_REQ (shift << 51) -#define L3_STATUS_0_IVATA_REQ (shift << 54) -#define L3_STATUS_0_SGXTA_REQ (shift << 55) -#define L3_STATUS_0_SGXTA_SERROR (shift << 56) -#define L3_STATUS_0_GPMCTA_SERROR (shift << 57) -#define L3_STATUS_0_L4CORETA_REQ (shift << 58) -#define L3_STATUS_0_L4PERTA_REQ (shift << 59) -#define L3_STATUS_0_L4EMUTA_REQ (shift << 60) -#define L3_STATUS_0_MAD2DTA_REQ (shift << 61) - -#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \ - | L3_STATUS_0_MPUIA_RSP \ - | L3_STATUS_0_IVAIA_BRST \ - | L3_STATUS_0_IVAIA_RSP \ - | L3_STATUS_0_SGXIA_BRST \ - | L3_STATUS_0_SGXIA_RSP \ - | L3_STATUS_0_CAMIA_BRST \ - | L3_STATUS_0_CAMIA_RSP \ - | L3_STATUS_0_DISPIA_BRST \ - | L3_STATUS_0_DISPIA_RSP \ - | L3_STATUS_0_DMARDIA_BRST \ - | L3_STATUS_0_DMARDIA_RSP \ - | L3_STATUS_0_DMAWRIA_BRST \ - | L3_STATUS_0_DMAWRIA_RSP \ - | L3_STATUS_0_USBOTGIA_BRST \ - | L3_STATUS_0_USBOTGIA_RSP \ - | L3_STATUS_0_USBHOSTIA_BRST \ - | L3_STATUS_0_SMSTA_REQ \ - | L3_STATUS_0_GPMCTA_REQ \ - | L3_STATUS_0_OCMRAMTA_REQ \ - | L3_STATUS_0_OCMROMTA_REQ \ - | L3_STATUS_0_IVATA_REQ \ - | L3_STATUS_0_SGXTA_REQ \ - | L3_STATUS_0_L4CORETA_REQ \ - | L3_STATUS_0_L4PERTA_REQ \ - | L3_STATUS_0_L4EMUTA_REQ \ - | L3_STATUS_0_MAD2DTA_REQ) - -#define L3_SI_FLAG_STATUS_1 0x530 - -#define L3_STATUS_1_MPU_DATAIA (1 << 0) -#define L3_STATUS_1_DAPIA0 (1 << 3) -#define L3_STATUS_1_DAPIA1 (1 << 4) -#define L3_STATUS_1_IVAIA (1 << 6) - -#define L3_PM_ERROR_LOG 0x020 -#define L3_PM_CONTROL 0x028 -#define L3_PM_ERROR_CLEAR_SINGLE 0x030 -#define L3_PM_ERROR_CLEAR_MULTI 0x038 -#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n)) -#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n)) -#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n)) -#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n)) - -/* L3 error log bit fields. Common for IA and TA */ -#define L3_ERROR_LOG_CODE 24 -#define L3_ERROR_LOG_INITID 8 -#define L3_ERROR_LOG_CMD 0 - -/* L3 agent status bit fields. */ -#define L3_AGENT_STATUS_CLEAR_IA 0x10000000 -#define L3_AGENT_STATUS_CLEAR_TA 0x01000000 - -#define OMAP34xx_IRQ_L3_APP 10 -#define L3_APPLICATION_ERROR 0x0 -#define L3_DEBUG_ERROR 0x1 - -enum omap3_l3_initiator_id { - /* LCD has 1 ID */ - OMAP_L3_LCD = 29, - /* SAD2D has 1 ID */ - OMAP_L3_SAD2D = 28, - /* MPU has 5 IDs */ - OMAP_L3_IA_MPU_SS_1 = 27, - OMAP_L3_IA_MPU_SS_2 = 26, - OMAP_L3_IA_MPU_SS_3 = 25, - OMAP_L3_IA_MPU_SS_4 = 24, - OMAP_L3_IA_MPU_SS_5 = 23, - /* IVA2.2 SS has 3 IDs*/ - OMAP_L3_IA_IVA_SS_1 = 22, - OMAP_L3_IA_IVA_SS_2 = 21, - OMAP_L3_IA_IVA_SS_3 = 20, - /* IVA 2.2 SS DMA has 6 IDS */ - OMAP_L3_IA_IVA_SS_DMA_1 = 19, - OMAP_L3_IA_IVA_SS_DMA_2 = 18, - OMAP_L3_IA_IVA_SS_DMA_3 = 17, - OMAP_L3_IA_IVA_SS_DMA_4 = 16, - OMAP_L3_IA_IVA_SS_DMA_5 = 15, - OMAP_L3_IA_IVA_SS_DMA_6 = 14, - /* SGX has 1 ID */ - OMAP_L3_IA_SGX = 13, - /* CAM has 3 ID */ - OMAP_L3_IA_CAM_1 = 12, - OMAP_L3_IA_CAM_2 = 11, - OMAP_L3_IA_CAM_3 = 10, - /* DAP has 1 ID */ - OMAP_L3_IA_DAP = 9, - /* SDMA WR has 2 IDs */ - OMAP_L3_SDMA_WR_1 = 8, - OMAP_L3_SDMA_WR_2 = 7, - /* SDMA RD has 4 IDs */ - OMAP_L3_SDMA_RD_1 = 6, - OMAP_L3_SDMA_RD_2 = 5, - OMAP_L3_SDMA_RD_3 = 4, - OMAP_L3_SDMA_RD_4 = 3, - /* HSUSB OTG has 1 ID */ - OMAP_L3_USBOTG = 2, - /* HSUSB HOST has 1 ID */ - OMAP_L3_USBHOST = 1, -}; - -enum omap3_l3_code { - OMAP_L3_CODE_NOERROR = 0, - OMAP_L3_CODE_UNSUP_CMD = 1, - OMAP_L3_CODE_ADDR_HOLE = 2, - OMAP_L3_CODE_PROTECT_VIOLATION = 3, - OMAP_L3_CODE_IN_BAND_ERR = 4, - /* codes 5 and 6 are reserved */ - OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7, - OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8, - /* codes 9 - 15 are also reserved */ -}; - -struct omap3_l3 { - struct device *dev; - struct clk *ick; - - /* memory base*/ - void __iomem *rt; - - int debug_irq; - int app_irq; - - /* true when and inband functional error occurs */ - unsigned inband:1; -}; - -/* offsets for l3 agents in order with the Flag status register */ -static unsigned int omap3_l3_app_bases[] = { - /* MPU IA */ - 0x1400, - 0x1400, - 0x1400, - /* RESERVED */ - 0, - 0, - 0, - /* IVA 2.2 IA */ - 0x1800, - 0x1800, - 0x1800, - /* SGX IA */ - 0x1c00, - 0x1c00, - /* RESERVED */ - 0, - /* CAMERA IA */ - 0x5800, - 0x5800, - 0x5800, - /* DISPLAY IA */ - 0x5400, - 0x5400, - /* RESERVED */ - 0, - /*SDMA RD IA */ - 0x4c00, - 0x4c00, - /* RESERVED */ - 0, - /* SDMA WR IA */ - 0x5000, - 0x5000, - /* RESERVED */ - 0, - /* USB OTG IA */ - 0x4400, - 0x4400, - 0x4400, - /* USB HOST IA */ - 0x4000, - 0x4000, - /* RESERVED */ - 0, - 0, - 0, - 0, - /* SAD2D IA */ - 0x3000, - 0x3000, - 0x3000, - /* RESERVED */ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - /* SMA TA */ - 0x2000, - /* GPMC TA */ - 0x2400, - /* OCM RAM TA */ - 0x2800, - /* OCM ROM TA */ - 0x2C00, - /* L4 CORE TA */ - 0x6800, - /* L4 PER TA */ - 0x6c00, - /* IVA 2.2 TA */ - 0x6000, - /* SGX TA */ - 0x6400, - /* L4 EMU TA */ - 0x7000, - /* GPMC TA */ - 0x2400, - /* L4 CORE TA */ - 0x6800, - /* L4 PER TA */ - 0x6c00, - /* L4 EMU TA */ - 0x7000, - /* MAD2D TA */ - 0x3400, - /* RESERVED */ - 0, - 0, -}; - -static unsigned int omap3_l3_debug_bases[] = { - /* MPU DATA IA */ - 0x1400, - /* RESERVED */ - 0, - 0, - /* DAP IA */ - 0x5c00, - 0x5c00, - /* RESERVED */ - 0, - /* IVA 2.2 IA */ - 0x1800, - /* REST RESERVED */ -}; - -static u32 *omap3_l3_bases[] = { - omap3_l3_app_bases, - omap3_l3_debug_bases, -}; - -/* - * REVISIT define __raw_readll/__raw_writell here, but move them to - * <asm/io.h> at some point - */ -#define __raw_writell(v, a) (__chk_io_ptr(a), \ - *(volatile u64 __force *)(a) = (v)) -#define __raw_readll(a) (__chk_io_ptr(a), \ - *(volatile u64 __force *)(a)) - -#endif diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index d52651a05da..d992db8ff0b 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -29,145 +29,9 @@ #include <linux/usb.h> #include <plat/usb.h> -#include "control.h" - -/* OMAP control module register for UTMI PHY */ -#define CONTROL_DEV_CONF 0x300 -#define PHY_PD 0x1 - -#define USBOTGHS_CONTROL 0x33c -#define AVALID BIT(0) -#define BVALID BIT(1) -#define VBUSVALID BIT(2) -#define SESSEND BIT(3) -#define IDDIG BIT(4) - -static struct clk *phyclk, *clk48m, *clk32k; -static void __iomem *ctrl_base; -static int usbotghs_control; - -int omap4430_phy_init(struct device *dev) -{ - ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K); - if (!ctrl_base) { - pr_err("control module ioremap failed\n"); - return -ENOMEM; - } - /* Power down the phy */ - __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); - - if (!dev) { - iounmap(ctrl_base); - return 0; - } - - phyclk = clk_get(dev, "ocp2scp_usb_phy_ick"); - if (IS_ERR(phyclk)) { - dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n"); - iounmap(ctrl_base); - return PTR_ERR(phyclk); - } - - clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m"); - if (IS_ERR(clk48m)) { - dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n"); - clk_put(phyclk); - iounmap(ctrl_base); - return PTR_ERR(clk48m); - } - - clk32k = clk_get(dev, "usb_phy_cm_clk32k"); - if (IS_ERR(clk32k)) { - dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n"); - clk_put(phyclk); - clk_put(clk48m); - iounmap(ctrl_base); - return PTR_ERR(clk32k); - } - return 0; -} - -int omap4430_phy_set_clk(struct device *dev, int on) -{ - static int state; - - if (on && !state) { - /* Enable the phy clocks */ - clk_enable(phyclk); - clk_enable(clk48m); - clk_enable(clk32k); - state = 1; - } else if (state) { - /* Disable the phy clocks */ - clk_disable(phyclk); - clk_disable(clk48m); - clk_disable(clk32k); - state = 0; - } - return 0; -} - -int omap4430_phy_power(struct device *dev, int ID, int on) -{ - if (on) { - if (ID) - /* enable VBUS valid, IDDIG groung */ - __raw_writel(AVALID | VBUSVALID, ctrl_base + - USBOTGHS_CONTROL); - else - /* - * Enable VBUS Valid, AValid and IDDIG - * high impedance - */ - __raw_writel(IDDIG | AVALID | VBUSVALID, - ctrl_base + USBOTGHS_CONTROL); - } else { - /* Enable session END and IDIG to high impedance. */ - __raw_writel(SESSEND | IDDIG, ctrl_base + - USBOTGHS_CONTROL); - } - return 0; -} - -int omap4430_phy_suspend(struct device *dev, int suspend) -{ - if (suspend) { - /* Disable the clocks */ - omap4430_phy_set_clk(dev, 0); - /* Power down the phy */ - __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); - - /* save the context */ - usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL); - } else { - /* Enable the internel phy clcoks */ - omap4430_phy_set_clk(dev, 1); - /* power on the phy */ - if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) { - __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF); - mdelay(200); - } - - /* restore the context */ - __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL); - } - - return 0; -} - -int omap4430_phy_exit(struct device *dev) -{ - if (ctrl_base) - iounmap(ctrl_base); - if (phyclk) - clk_put(phyclk); - if (clk48m) - clk_put(clk48m); - if (clk32k) - clk_put(clk32k); - return 0; -} +#include "soc.h" +#include "control.h" void am35x_musb_reset(void) { diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index d8f6dbf45d1..45ad7f74f35 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c @@ -64,25 +64,22 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, } oh = omap_hwmod_lookup(opp_def->hwmod_name); if (!oh || !oh->od) { - pr_debug("%s: no hwmod or odev for %s, [%d] " - "cannot add OPPs.\n", __func__, - opp_def->hwmod_name, i); + pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n", + __func__, opp_def->hwmod_name, i); continue; } dev = &oh->od->pdev->dev; r = opp_add(dev, opp_def->freq, opp_def->u_volt); if (r) { - dev_err(dev, "%s: add OPP %ld failed for %s [%d] " - "result=%d\n", - __func__, opp_def->freq, - opp_def->hwmod_name, i, r); + dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n", + __func__, opp_def->freq, + opp_def->hwmod_name, i, r); } else { if (!opp_def->default_available) r = opp_disable(dev, opp_def->freq); if (r) - dev_err(dev, "%s: disable %ld failed for %s " - "[%d] result=%d\n", + dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n", __func__, opp_def->freq, opp_def->hwmod_name, i, r); } diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c index 5037e76e4e2..a9e8cf21705 100644 --- a/arch/arm/mach-omap2/opp2420_data.c +++ b/arch/arm/mach-omap2/opp2420_data.c @@ -28,7 +28,7 @@ * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/ */ -#include <plat/hardware.h> +#include <linux/kernel.h> #include "opp2xxx.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c index 750805c528d..0e75ec3e114 100644 --- a/arch/arm/mach-omap2/opp2430_data.c +++ b/arch/arm/mach-omap2/opp2430_data.c @@ -26,7 +26,7 @@ * This is technically part of the OMAP2xxx clock code. */ -#include <plat/hardware.h> +#include <linux/kernel.h> #include "opp2xxx.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c index d95f3f945d4..75cef5f67a8 100644 --- a/arch/arm/mach-omap2/opp3xxx_data.c +++ b/arch/arm/mach-omap2/opp3xxx_data.c @@ -19,8 +19,6 @@ */ #include <linux/module.h> -#include <plat/cpu.h> - #include "control.h" #include "omap_opp_data.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c index c95415da23c..a9fd6d5fe79 100644 --- a/arch/arm/mach-omap2/opp4xxx_data.c +++ b/arch/arm/mach-omap2/opp4xxx_data.c @@ -20,8 +20,7 @@ */ #include <linux/module.h> -#include <plat/cpu.h> - +#include "soc.h" #include "control.h" #include "omap_opp_data.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 814bcd90159..3e1345fc071 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -28,7 +28,6 @@ #include <linux/slab.h> #include <plat/clock.h> -#include <plat/board.h> #include "powerdomain.h" #include "clockdomain.h" #include <plat/dmtimer.h> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 9cb5cede0f5..939bd6f70b5 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -203,8 +203,8 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, bootup_volt = opp_get_voltage(opp); rcu_read_unlock(); if (!bootup_volt) { - pr_err("%s: unable to find voltage corresponding " - "to the bootup OPP for vdd_%s\n", __func__, vdd_name); + pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n", + __func__, vdd_name); goto exit; } diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 2edeffc923a..8af6cd6ac33 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -29,6 +29,7 @@ #include <linux/irq.h> #include <linux/time.h> #include <linux/gpio.h> +#include <linux/platform_data/gpio-omap.h> #include <asm/mach/time.h> #include <asm/mach/irq.h> @@ -38,9 +39,6 @@ #include <plat/clock.h> #include <plat/sram.h> #include <plat/dma.h> -#include <plat/board.h> - -#include <mach/irqs.h> #include "common.h" #include "prm2xxx_3xxx.h" @@ -352,16 +350,6 @@ int __init omap2_pm_init(void) prcm_setup_regs(); - /* Hack to prevent MPU retention when STI console is enabled. */ - { - const struct omap_sti_console_config *sti; - - sti = omap_get_config(OMAP_TAG_STI_CONSOLE, - struct omap_sti_console_config); - if (sti != NULL && sti->enable) - sti_console_enabled = 1; - } - /* * We copy the assembler sleep/wakeup routines to SRAM. * These routines need to be in SRAM as that's the only diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 05bd8f02723..ba670db1fd3 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -28,6 +28,8 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/slab.h> +#include <linux/platform_data/gpio-omap.h> + #include <trace/events/power.h> #include <asm/suspend.h> @@ -389,9 +391,8 @@ restore: list_for_each_entry(pwrst, &pwrst_list, node) { state = pwrdm_read_prev_pwrst(pwrst->pwrdm); if (state > pwrst->next_state) { - pr_info("Powerdomain (%s) didn't enter " - "target state %d\n", - pwrst->pwrdm->name, pwrst->next_state); + pr_info("Powerdomain (%s) didn't enter target state %d\n", + pwrst->pwrdm->name, pwrst->next_state); ret = -1; } omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); @@ -731,8 +732,7 @@ int __init omap3_pm_init(void) omap3_secure_ram_storage = kmalloc(0x803F, GFP_KERNEL); if (!omap3_secure_ram_storage) - pr_err("Memory allocation failed when " - "allocating for secure sram context\n"); + pr_err("Memory allocation failed when allocating for secure sram context\n"); local_irq_disable(); local_fiq_disable(); diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index ea24174f570..04922d14906 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -69,9 +69,8 @@ static int omap4_pm_suspend(void) list_for_each_entry(pwrst, &pwrst_list, node) { state = pwrdm_read_prev_pwrst(pwrst->pwrdm); if (state > pwrst->next_state) { - pr_info("Powerdomain (%s) didn't enter " - "target state %d\n", - pwrst->pwrdm->name, pwrst->next_state); + pr_info("Powerdomain (%s) didn't enter target state %d\n", + pwrst->pwrdm->name, pwrst->next_state); ret = -1; } omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); @@ -189,8 +188,7 @@ int __init omap4_pm_init(void) ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); if (ret) { - pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 " - "wakeup dependency\n"); + pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); goto err2; } diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 69b36e185e9..1678a328423 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -28,11 +28,13 @@ #include "prm44xx.h" #include <asm/cpu.h> -#include <plat/cpu.h> + +#include <plat/prcm.h> + #include "powerdomain.h" #include "clockdomain.h" -#include <plat/prcm.h> +#include "soc.h" #include "pm.h" #define PWRDM_TRACE_STATES_FLAG (1<<31) @@ -339,8 +341,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) if (!pwrdm || !clkdm) return -EINVAL; - pr_debug("powerdomain: associating clockdomain %s with powerdomain " - "%s\n", clkdm->name, pwrdm->name); + pr_debug("powerdomain: %s: associating clockdomain %s\n", + pwrdm->name, clkdm->name); for (i = 0; i < PWRDM_MAX_CLKDMS; i++) { if (!pwrdm->pwrdm_clkdms[i]) @@ -354,8 +356,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) } if (i == PWRDM_MAX_CLKDMS) { - pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for " - "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name); + pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS for clkdm %s\n", + pwrdm->name, clkdm->name); WARN_ON(1); ret = -ENOMEM; goto pac_exit; @@ -387,16 +389,16 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) if (!pwrdm || !clkdm) return -EINVAL; - pr_debug("powerdomain: dissociating clockdomain %s from powerdomain " - "%s\n", clkdm->name, pwrdm->name); + pr_debug("powerdomain: %s: dissociating clockdomain %s\n", + pwrdm->name, clkdm->name); for (i = 0; i < PWRDM_MAX_CLKDMS; i++) if (pwrdm->pwrdm_clkdms[i] == clkdm) break; if (i == PWRDM_MAX_CLKDMS) { - pr_debug("powerdomain: clkdm %s not associated with pwrdm " - "%s ?!\n", clkdm->name, pwrdm->name); + pr_debug("powerdomain: %s: clkdm %s not associated?!\n", + pwrdm->name, clkdm->name); ret = -ENOENT; goto pdc_exit; } @@ -485,7 +487,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) if (!(pwrdm->pwrsts & (1 << pwrst))) return -EINVAL; - pr_debug("powerdomain: setting next powerstate for %s to %0x\n", + pr_debug("powerdomain: %s: setting next powerstate to %0x\n", pwrdm->name, pwrst); if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) { @@ -587,7 +589,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst))) return -EINVAL; - pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n", + pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n", pwrdm->name, pwrst); if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst) @@ -624,8 +626,8 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst))) return -EINVAL; - pr_debug("powerdomain: setting next memory powerstate for domain %s " - "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst); + pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-ON to %0x\n", + pwrdm->name, bank, pwrst); if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst) ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst); @@ -662,8 +664,8 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst))) return -EINVAL; - pr_debug("powerdomain: setting next memory powerstate for domain %s " - "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst); + pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-RET to %0x\n", + pwrdm->name, bank, pwrst); if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst) ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst); @@ -841,7 +843,7 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) * warn & fail if it is not ON. */ - pr_debug("powerdomain: clearing previous power state reg for %s\n", + pr_debug("powerdomain: %s: clearing previous power state reg\n", pwrdm->name); if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst) @@ -871,8 +873,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) return ret; - pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", - pwrdm->name); + pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name); if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar) ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm); @@ -901,8 +902,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) return ret; - pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", - pwrdm->name); + pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name); if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar) ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm); diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c index 0f0a9f1592f..3950ccfe5f4 100644 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -122,8 +122,8 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) udelay(1); if (c > PWRDM_TRANSITION_BAILOUT) { - printk(KERN_ERR "powerdomain: waited too long for " - "powerdomain %s to complete transition\n", pwrdm->name); + pr_err("powerdomain: %s: waited too long to complete transition\n", + pwrdm->name); return -EAGAIN; } diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index 601325b852a..aeac6f35ca1 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -198,8 +198,8 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) udelay(1); if (c > PWRDM_TRANSITION_BAILOUT) { - printk(KERN_ERR "powerdomain: waited too long for " - "powerdomain %s to complete transition\n", pwrdm->name); + pr_err("powerdomain: %s: waited too long to complete transition\n", + pwrdm->name); return -EAGAIN; } diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index bb883e46307..8b23d234fb5 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -15,11 +15,9 @@ #include <linux/init.h> #include <linux/bug.h> -#include <plat/cpu.h> - +#include "soc.h" #include "powerdomain.h" #include "powerdomains2xxx_3xxx_data.h" - #include "prcm-common.h" #include "prm2xxx_3xxx.h" #include "prm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 053e24ed3c4..0f51e034e0a 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -27,7 +27,6 @@ #include "common.h" #include <plat/prcm.h> -#include <plat/irqs.h> #include "clock.h" #include "clock2xxx.h" @@ -140,11 +139,11 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, MAX_MODULE_ENABLE_WAIT, i); if (i < MAX_MODULE_ENABLE_WAIT) - pr_debug("cm: Module associated with clock %s ready after %d " - "loops\n", name, i); + pr_debug("cm: Module associated with clock %s ready after %d loops\n", + name, i); else - pr_err("cm: Module associated with clock %s didn't enable in " - "%d tries\n", name, MAX_MODULE_ENABLE_WAIT); + pr_err("cm: Module associated with clock %s didn't enable in %d tries\n", + name, MAX_MODULE_ENABLE_WAIT); return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; }; diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index a0309dea679..9529984d8d2 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -17,11 +17,10 @@ #include <linux/io.h> #include <linux/irq.h> -#include "common.h" -#include <plat/cpu.h> #include <plat/prcm.h> -#include <plat/irqs.h> +#include "soc.h" +#include "common.h" #include "vp.h" #include "prm2xxx_3xxx.h" @@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { .nr_regs = 1, .irqs = omap3_prcm_irqs, .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs), - .irq = INT_34XX_PRCM_MPU_IRQ, + .irq = 11 + OMAP_INTC_START, .read_pending_irqs = &omap3xxx_prm_read_pending_irqs, .ocp_barrier = &omap3xxx_prm_ocp_barrier, .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index bb727c2d933..f0c4d5f4a17 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -17,10 +17,9 @@ #include <linux/err.h> #include <linux/io.h> -#include <plat/cpu.h> -#include <plat/irqs.h> #include <plat/prcm.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "vp.h" @@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { .nr_regs = 2, .irqs = omap4_prcm_irqs, .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), - .irq = OMAP44XX_IRQ_PRCM, + .irq = 11 + OMAP44XX_IRQ_GIC_START, .read_pending_irqs = &omap44xx_prm_read_pending_irqs, .ocp_barrier = &omap44xx_prm_ocp_barrier, .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 03b126d9ad9..6b4d332be2f 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -26,7 +26,6 @@ #include <plat/common.h> #include <plat/prcm.h> -#include <plat/irqs.h> #include "prm2xxx_3xxx.h" #include "prm44xx.h" diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 1133bb2f632..73e55e48532 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -24,11 +24,11 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clock.h> #include <plat/sram.h> #include <plat/sdrc.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "prm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index c1b93c752d7..0405c819080 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -29,11 +29,11 @@ #include <plat/omap-serial.h> #include "common.h" -#include <plat/board.h> #include <plat/dma.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> #include <plat/omap-pm.h> +#include <plat/serial.h> #include "prm2xxx_3xxx.h" #include "pm.h" @@ -81,8 +81,9 @@ static struct omap_uart_port_info omap_serial_default_info[] __initdata = { }; #ifdef CONFIG_PM -static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) +static void omap_uart_enable_wakeup(struct device *dev, bool enable) { + struct platform_device *pdev = to_platform_device(dev); struct omap_device *od = to_omap_device(pdev); if (!od) @@ -99,15 +100,17 @@ static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) * in Smartidle Mode When Configured for DMA Operations. * WA: configure uart in force idle mode. */ -static void omap_uart_set_noidle(struct platform_device *pdev) +static void omap_uart_set_noidle(struct device *dev) { + struct platform_device *pdev = to_platform_device(dev); struct omap_device *od = to_omap_device(pdev); omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); } -static void omap_uart_set_smartidle(struct platform_device *pdev) +static void omap_uart_set_smartidle(struct device *dev) { + struct platform_device *pdev = to_platform_device(dev); struct omap_device *od = to_omap_device(pdev); u8 idlemode; @@ -120,10 +123,10 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) } #else -static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) +static void omap_uart_enable_wakeup(struct device *dev, bool enable) {} -static void omap_uart_set_noidle(struct platform_device *pdev) {} -static void omap_uart_set_smartidle(struct platform_device *pdev) {} +static void omap_uart_set_noidle(struct device *dev) {} +static void omap_uart_set_smartidle(struct device *dev) {} #endif /* CONFIG_PM */ #ifdef CONFIG_OMAP_MUX @@ -229,9 +232,8 @@ static int __init omap_serial_early_init(void) if (console_loglevel >= 10) { uart_debug = true; - pr_info("%s used as console in debug mode" - " uart%d clocks will not be" - " gated", uart_name, uart->num); + pr_info("%s used as console in debug mode: uart%d clocks will not be gated", + uart_name, uart->num); } if (cmdline_find_option("no_console_suspend")) @@ -304,6 +306,9 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, omap_up.dma_rx_timeout = info->dma_rx_timeout; omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate; omap_up.autosuspend_timeout = info->autosuspend_timeout; + omap_up.DTR_gpio = info->DTR_gpio; + omap_up.DTR_inverted = info->DTR_inverted; + omap_up.DTR_present = info->DTR_present; pdata = &omap_up; pdata_size = sizeof(struct omap_uart_port_info); @@ -313,8 +318,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size, NULL, 0, false); - WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", - name, oh->name); + if (IS_ERR(pdev)) { + WARN(1, "Could not build omap_device for %s: %s.\n", name, + oh->name); + return; + } if ((console_uart_id == bdata->id) && no_console_suspend) omap_device_disable_idle_on_suspend(pdev); diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S index d4bf904d84a..ce0ccd26efb 100644 --- a/arch/arm/mach-omap2/sleep24xx.S +++ b/arch/arm/mach-omap2/sleep24xx.S @@ -28,8 +28,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#include <plat/omap24xx.h> - +#include "omap24xx.h" #include "sdrc.h" /* First address of reserved address space? apparently valid for OMAP2 & 3 */ diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 1f62f23673f..506987979c1 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -26,9 +26,9 @@ #include <asm/assembler.h> -#include <plat/hardware.h> #include <plat/sram.h> +#include "omap34xx.h" #include "iomap.h" #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S index 91e71d8f46f..88ff83a0942 100644 --- a/arch/arm/mach-omap2/sleep44xx.S +++ b/arch/arm/mach-omap2/sleep44xx.S @@ -14,10 +14,10 @@ #include <asm/memory.h> #include <asm/hardware/cache-l2x0.h> -#include <plat/omap44xx.h> -#include <mach/omap-secure.h> +#include "omap-secure.h" #include "common.h" +#include "omap44xx.h" #include "omap4-sar-layout.h" #if defined(CONFIG_SMP) && defined(CONFIG_PM) diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h new file mode 100644 index 00000000000..fc9b96daf85 --- /dev/null +++ b/arch/arm/mach-omap2/soc.h @@ -0,0 +1,7 @@ +#include <plat/cpu.h> +#include "omap24xx.h" +#include "omap34xx.h" +#include "omap44xx.h" +#include "ti81xx.h" +#include "am33xx.h" +#include "omap54xx.h" diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index d033a65f4e4..cbeae56b56a 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -104,16 +104,15 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL); if (!sr_data) { - pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n", - __func__, oh->name); + pr_err("%s: Unable to allocate memory for %s sr_data\n", + __func__, oh->name); return -ENOMEM; } sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr; if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) { - pr_err("%s: No voltage domain specified for %s." - "Cannot initialize\n", __func__, - oh->name); + pr_err("%s: No voltage domain specified for %s. Cannot initialize\n", + __func__, oh->name); goto exit; } @@ -131,8 +130,8 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) omap_voltage_get_volttable(sr_data->voltdm, &volt_data); if (!volt_data) { - pr_warning("%s: No Voltage table registered fo VDD%d." - "Something really wrong\n\n", __func__, i + 1); + pr_err("%s: No Voltage table registered for VDD%d\n", + __func__, i + 1); goto exit; } diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index ee0bfcc1410..8f7326cd435 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S @@ -32,8 +32,7 @@ #include <asm/assembler.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index d4d39ef0476..b140d657852 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -32,8 +32,7 @@ #include <asm/assembler.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index df5a21322b0..2d0ceaa23fb 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -29,8 +29,7 @@ #include <asm/assembler.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" #include "sdrc.h" #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h new file mode 100644 index 00000000000..8f9843f7842 --- /dev/null +++ b/arch/arm/mach-omap2/ti81xx.h @@ -0,0 +1,27 @@ +/* + * This file contains the address data for various TI81XX modules. + * + * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_TI81XX_H +#define __ASM_ARCH_TI81XX_H + +#define L4_SLOW_TI81XX_BASE 0x48000000 + +#define TI81XX_SCM_BASE 0x48140000 +#define TI81XX_CTRL_BASE TI81XX_SCM_BASE +#define TI81XX_PRCM_BASE 0x48180000 + +#define TI81XX_ARM_INTC_BASE 0x48200000 + +#endif /* __ASM_ARCH_TI81XX_H */ diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2ba4f57dda8..8847d6eb231 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -36,16 +36,20 @@ #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/slab.h> +#include <linux/of.h> #include <asm/mach/time.h> -#include <plat/dmtimer.h> #include <asm/smp_twd.h> #include <asm/sched_clock.h> -#include "common.h" + +#include <asm/arch_timer.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> +#include <plat/dmtimer.h> #include <plat/omap-pm.h> +#include "soc.h" +#include "common.h" #include "powerdomain.h" /* Parent clocks, eventually these will come from the clock framework */ @@ -69,6 +73,11 @@ #define OMAP3_SECURE_TIMER 1 #endif +#define REALTIME_COUNTER_BASE 0x48243200 +#define INCREMENTER_NUMERATOR_OFFSET 0x10 +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 +#define NUMERATOR_DENUMERATOR_MASK 0xfffff000 + /* Clockevent code */ static struct omap_dm_timer clkev; @@ -211,7 +220,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); BUG_ON(res); - omap2_gp_timer_irq.dev_id = (void *)&clkev; + omap2_gp_timer_irq.dev_id = &clkev; setup_irq(clkev.irq, &omap2_gp_timer_irq); __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); @@ -346,6 +355,84 @@ static void __init omap2_clocksource_init(int gptimer_id, omap2_gptimer_clocksource_init(gptimer_id, fck_source); } +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER +/* + * The realtime counter also called master counter, is a free-running + * counter, which is related to real time. It produces the count used + * by the CPU local timer peripherals in the MPU cluster. The timer counts + * at a rate of 6.144 MHz. Because the device operates on different clocks + * in different power modes, the master counter shifts operation between + * clocks, adjusting the increment per clock in hardware accordingly to + * maintain a constant count rate. + */ +static void __init realtime_counter_init(void) +{ + void __iomem *base; + static struct clk *sys_clk; + unsigned long rate; + unsigned int reg, num, den; + + base = ioremap(REALTIME_COUNTER_BASE, SZ_32); + if (!base) { + pr_err("%s: ioremap failed\n", __func__); + return; + } + sys_clk = clk_get(NULL, "sys_clkin_ck"); + if (!sys_clk) { + pr_err("%s: failed to get system clock handle\n", __func__); + iounmap(base); + return; + } + + rate = clk_get_rate(sys_clk); + /* Numerator/denumerator values refer TRM Realtime Counter section */ + switch (rate) { + case 1200000: + num = 64; + den = 125; + break; + case 1300000: + num = 768; + den = 1625; + break; + case 19200000: + num = 8; + den = 25; + break; + case 2600000: + num = 384; + den = 1625; + break; + case 2700000: + num = 256; + den = 1125; + break; + case 38400000: + default: + /* Program it for 38.4 MHz */ + num = 4; + den = 25; + break; + } + + /* Program numerator and denumerator registers */ + reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + NUMERATOR_DENUMERATOR_MASK; + reg |= num; + __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); + + reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + NUMERATOR_DENUMERATOR_MASK; + reg |= den; + __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); + + iounmap(base); +} +#else +static inline void __init realtime_counter_init(void) +{} +#endif + #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ clksrc_nr, clksrc_src) \ static void __init omap##name##_timer_init(void) \ @@ -380,8 +467,7 @@ OMAP_SYS_TIMER(3_am33xx) #ifdef CONFIG_ARCH_OMAP4 #ifdef CONFIG_LOCAL_TIMERS static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, - OMAP44XX_LOCAL_TWD_BASE, - OMAP44XX_IRQ_LOCALTIMER); + OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START); #endif static void __init omap4_timer_init(void) @@ -393,6 +479,11 @@ static void __init omap4_timer_init(void) if (omap_rev() != OMAP4430_REV_ES1_0) { int err; + if (of_have_populated_dt()) { + twd_local_timer_of_register(); + return; + } + err = twd_local_timer_register(&twd_local_timer); if (err) pr_err("twd_local_timer_register failed %d\n", err); @@ -403,7 +494,18 @@ OMAP_SYS_TIMER(4) #endif #ifdef CONFIG_SOC_OMAP5 -OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE) +static void __init omap5_timer_init(void) +{ + int err; + + omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); + omap2_clocksource_init(2, OMAP4_MPU_SOURCE); + realtime_counter_init(); + + err = arch_timer_of_register(); + if (err) + pr_err("%s: arch_timer_register failed %d\n", __func__, err); +} OMAP_SYS_TIMER(5) #endif diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index db5ff664237..45f77413c21 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -29,6 +29,7 @@ #include <plat/i2c.h> #include <plat/usb.h> +#include "soc.h" #include "twl-common.h" #include "pm.h" #include "voltage.h" @@ -39,16 +40,6 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = { .flags = I2C_CLIENT_WAKE, }; -static struct i2c_board_info __initdata omap4_i2c1_board_info[] = { - { - .addr = 0x48, - .flags = I2C_CLIENT_WAKE, - }, - { - I2C_BOARD_INFO("twl6040", 0x4b), - }, -}; - #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) static int twl_set_voltage(void *data, int target_uV) { @@ -78,30 +69,25 @@ void __init omap_pmic_init(int bus, u32 clkrate, void __init omap4_pmic_init(const char *pmic_type, struct twl4030_platform_data *pmic_data, - struct twl6040_platform_data *twl6040_data, int twl6040_irq) + struct i2c_board_info *devices, int nr_devices) { /* PMIC part*/ omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE); - strncpy(omap4_i2c1_board_info[0].type, pmic_type, - sizeof(omap4_i2c1_board_info[0].type)); - omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N; - omap4_i2c1_board_info[0].platform_data = pmic_data; - - /* TWL6040 audio IC part */ - omap4_i2c1_board_info[1].irq = twl6040_irq; - omap4_i2c1_board_info[1].platform_data = twl6040_data; - - omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2); + omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data); + /* Register additional devices on i2c1 bus if needed */ + if (devices) + i2c_register_board_info(1, devices, nr_devices); } void __init omap_pmic_late_init(void) { - /* Init the OMAP TWL parameters (if PMIC has been registered) */ - if (pmic_i2c_board_info.irq) - omap3_twl_init(); - if (omap4_i2c1_board_info[0].irq) - omap4_twl_init(); + /* Init the OMAP TWL parameters (if PMIC has been registerd) */ + if (!pmic_i2c_board_info.irq) + return; + + omap3_twl_init(); + omap4_twl_init(); } #if defined(CONFIG_ARCH_OMAP3) @@ -251,11 +237,6 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, #if defined(CONFIG_ARCH_OMAP4) static struct twl4030_usb_data omap4_usb_pdata = { - .phy_init = omap4430_phy_init, - .phy_exit = omap4430_phy_exit, - .phy_power = omap4430_phy_power, - .phy_set_clock = omap4430_phy_set_clk, - .phy_suspend = omap4430_phy_suspend, }; static struct regulator_init_data omap4_vdac_idata = { diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h index 8fe71cfd002..2256efe90cf 100644 --- a/arch/arm/mach-omap2/twl-common.h +++ b/arch/arm/mach-omap2/twl-common.h @@ -1,7 +1,7 @@ #ifndef __OMAP_PMIC_COMMON__ #define __OMAP_PMIC_COMMON__ -#include <plat/irqs.h> +#include "common.h" #define TWL_COMMON_PDATA_USB (1 << 0) #define TWL_COMMON_PDATA_BCI (1 << 1) @@ -32,6 +32,7 @@ struct twl4030_platform_data; struct twl6040_platform_data; +struct i2c_board_info; void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data); @@ -40,18 +41,18 @@ void omap_pmic_late_init(void); static inline void omap2_pmic_init(const char *pmic_type, struct twl4030_platform_data *pmic_data) { - omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data); + omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data); } static inline void omap3_pmic_init(const char *pmic_type, struct twl4030_platform_data *pmic_data) { - omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data); + omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data); } void omap4_pmic_init(const char *pmic_type, struct twl4030_platform_data *pmic_data, - struct twl6040_platform_data *audio_data, int twl6040_irq); + struct i2c_board_info *devices, int nr_devices); void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, u32 pdata_flags, u32 regulators_flags); diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index dde8a11f47d..ac95daaa470 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -25,8 +25,6 @@ #include <asm/io.h> -#include <mach/hardware.h> -#include <mach/irqs.h> #include <plat/usb.h> #include <plat/omap_device.h> diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index c4a57685666..51da21cb78f 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -23,14 +23,13 @@ #include <linux/clk.h> #include <linux/dma-mapping.h> #include <linux/io.h> - #include <linux/usb/musb.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/am35xx.h> #include <plat/usb.h> #include <plat/omap_device.h> + +#include "am35xx.h" + #include "mux.h" static struct musb_hdrc_config musb_config = { @@ -117,7 +116,4 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) dev->dma_mask = &musb_dmamask; dev->coherent_dma_mask = musb_dmamask; put_device(dev); - - if (cpu_is_omap44xx()) - omap4430_phy_init(dev); } diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 84da34f9a7c..880249b1701 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -12,8 +12,7 @@ #include <linux/init.h> #include <linux/bug.h> -#include <plat/cpu.h> - +#include "soc.h" #include "voltage.h" #include "vc.h" #include "prm-regbits-34xx.h" @@ -116,9 +115,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm, } if (!voltdm->pmic->uv_to_vsel) { - pr_err("%s: PMIC function to convert voltage in uV to" - "vsel not registered. Hence unable to scale voltage" - "for vdd_%s\n", __func__, voltdm->name); + pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n", + __func__, voltdm->name); return -ENODATA; } diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 4dc60e83e00..3ac8fe1d821 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -195,8 +195,8 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, return &voltdm->volt_data[i]; } - pr_notice("%s: Unable to match the current voltage with the voltage" - "table for vdd_%s\n", __func__, voltdm->name); + pr_notice("%s: Unable to match the current voltage with the voltage table for vdd_%s\n", + __func__, voltdm->name); return ERR_PTR(-ENODATA); } @@ -249,8 +249,8 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm, voltdm->scale = omap_vc_bypass_scale; return; default: - pr_warning("%s: Trying to change the method of voltage scaling" - "to an unsupported one!\n", __func__); + pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n", + __func__); } } @@ -331,8 +331,8 @@ int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm) if (!voltdm || !pwrdm) return -EINVAL; - pr_debug("voltagedomain: associating powerdomain %s with voltagedomain " - "%s\n", pwrdm->name, voltdm->name); + pr_debug("voltagedomain: %s: associating powerdomain %s\n", + voltdm->name, pwrdm->name); list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list); diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 0ac2caf1594..7283b7ed7de 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -16,7 +16,7 @@ #include <linux/err.h> -#include <plat/voltage.h> +#include <linux/platform_data/voltage-omap.h> #include "vc.h" #include "vp.h" diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c index d0103c80d04..63afbfed3cb 100644 --- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c @@ -18,9 +18,8 @@ #include <linux/err.h> #include <linux/init.h> +#include "soc.h" #include "common.h" -#include <plat/cpu.h> - #include "prm-regbits-34xx.h" #include "omap_opp_data.h" #include "voltage.h" diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c index f95c1bad9dc..85241b828c0 100644 --- a/arch/arm/mach-omap2/vp.c +++ b/arch/arm/mach-omap2/vp.c @@ -138,8 +138,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm, udelay(1); } if (timeout >= VP_TRANXDONE_TIMEOUT) { - pr_warning("%s: vdd_%s TRANXDONE timeout exceeded." - "Voltage change aborted", __func__, voltdm->name); + pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted", + __func__, voltdm->name); return -ETIMEDOUT; } @@ -157,9 +157,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm, omap_test_timeout(vp->common->ops->check_txdone(vp->id), VP_TRANXDONE_TIMEOUT, timeout); if (timeout >= VP_TRANXDONE_TIMEOUT) - pr_err("%s: vdd_%s TRANXDONE timeout exceeded." - "TRANXDONE never got set after the voltage update\n", - __func__, voltdm->name); + pr_err("%s: vdd_%s TRANXDONE timeout exceeded. TRANXDONE never got set after the voltage update\n", + __func__, voltdm->name); omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); @@ -176,8 +175,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm, } if (timeout >= VP_TRANXDONE_TIMEOUT) - pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying" - "to clear the TRANXDONE status\n", + pr_warn("%s: vdd_%s TRANXDONE timeout exceeded while trying to clear the TRANXDONE status\n", __func__, voltdm->name); /* Clear force bit */ @@ -257,8 +255,8 @@ void omap_vp_disable(struct voltagedomain *voltdm) /* If VP is already disabled, do nothing. Return */ if (!vp->enabled) { - pr_warning("%s: Trying to disable VP for vdd_%s when" - "it is already disabled\n", __func__, voltdm->name); + pr_warn("%s: Trying to disable VP for vdd_%s when it is already disabled\n", + __func__, voltdm->name); return; } |