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authorLennert Buytenhek <buytenh@wantstofly.org>2008-10-20 01:51:03 +0200
committerNicolas Pitre <nico@cam.org>2008-12-20 12:21:02 -0500
commit9569dae75f6f6987e79fa26cf6da3fc24006c996 (patch)
treeb5982f41aea6ccee37af54fc8f7750aaff7e0bff /arch/arm/mach-orion5x/include
parent6fd7c7fe72a46dfd227fe8db0c7b6863af90a982 (diff)
[ARM] Orion: share GPIO handling code
Split off Orion GPIO handling code into plat-orion/, and add support for multiple sets of (32) GPIO pins. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-orion5x/include')
-rw-r--r--arch/arm/mach-orion5x/include/mach/gpio.h26
-rw-r--r--arch/arm/mach-orion5x/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h6
3 files changed, 17 insertions, 19 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
index 65dc136a86f..a1a387b189a 100644
--- a/arch/arm/mach-orion5x/include/mach/gpio.h
+++ b/arch/arm/mach-orion5x/include/mach/gpio.h
@@ -2,18 +2,23 @@
* arch/arm/mach-orion5x/include/mach/gpio.h
*
* This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-extern int gpio_request(unsigned pin, const char *label);
-extern void gpio_free(unsigned pin);
-extern int gpio_direction_input(unsigned pin);
-extern int gpio_direction_output(unsigned pin, int value);
-extern int gpio_get_value(unsigned pin);
-extern void gpio_set_value(unsigned pin, int value);
-extern void orion5x_gpio_set_blink(unsigned pin, int blink);
-extern void gpio_display(void); /* debug */
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <mach/irqs.h>
+#include <plat/gpio.h>
+#include <asm-generic/gpio.h> /* cansleep wrappers */
+
+#define GPIO_MAX 32
+#define GPIO_OUT(pin) ORION5X_DEV_BUS_REG(0x100)
+#define GPIO_IO_CONF(pin) ORION5X_DEV_BUS_REG(0x104)
+#define GPIO_BLINK_EN(pin) ORION5X_DEV_BUS_REG(0x108)
+#define GPIO_IN_POL(pin) ORION5X_DEV_BUS_REG(0x10c)
+#define GPIO_DATA_IN(pin) ORION5X_DEV_BUS_REG(0x110)
static inline int gpio_to_irq(int pin)
{
@@ -25,4 +30,5 @@ static inline int irq_to_gpio(int irq)
return irq - IRQ_ORION5X_GPIO_START;
}
-#include <asm-generic/gpio.h> /* cansleep wrappers */
+
+#endif
diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h
index d5b0fbf6b96..a6fa9d8f12d 100644
--- a/arch/arm/mach-orion5x/include/mach/irqs.h
+++ b/arch/arm/mach-orion5x/include/mach/irqs.h
@@ -13,8 +13,6 @@
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
-#include "orion5x.h" /* need GPIO_MAX */
-
/*
* Orion Main Interrupt Controller
*/
@@ -54,7 +52,7 @@
* Orion General Purpose Pins
*/
#define IRQ_ORION5X_GPIO_START 32
-#define NR_GPIO_IRQS GPIO_MAX
+#define NR_GPIO_IRQS 32
#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 9f5ce1ce584..a8915081773 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -134,11 +134,6 @@
#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
-#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100)
-#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104)
-#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108)
-#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c)
-#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110)
#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114)
#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118)
#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c)
@@ -149,7 +144,6 @@
#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
-#define GPIO_MAX 32
/***************************************************************************
* Orion CPU Bridge Registers