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authorLennert Buytenhek <buytenh@wantstofly.org>2008-04-25 16:28:33 -0400
committerNicolas Pitre <nico@cam.org>2008-04-28 15:58:23 -0400
commit92b913b08b18faa487b0c744282fafd944446ade (patch)
tree1a20f86d3762ebafeb4aea172d35e23ef1ade34f /arch/arm/mach-orion5x/pci.c
parentfd153abb01c3fbcc47cd4ac3c0bc8801cfcc0009 (diff)
[ARM] Orion: fix ->map_irq() PCIe bus number check
The current orion5x board ->map_irq() routines check whether a given bus number lives on the PCIe controller by comparing it with the PCIe controller's primary bus number. This doesn't work in case there are multiple buses in the PCIe domain, i.e. if there exists a PCIe bridge on the primary PCIe bus. This patch adds a helper function (orion5x_pci_map_irq()) that returns the IRQ number for the given PCI device if that device has a hard-wired IRQ, or -1 otherwise, and makes each board's ->map_irq() function use this helper function. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-orion5x/pci.c')
-rw-r--r--arch/arm/mach-orion5x/pci.c20
1 files changed, 14 insertions, 6 deletions
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index fdf99fca85b..9d5d39fa19c 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -41,11 +41,6 @@ void __init orion5x_pcie_id(u32 *dev, u32 *rev)
*rev = orion_pcie_rev(PCIE_BASE);
}
-int __init orion5x_pcie_local_bus_nr(void)
-{
- return orion_pcie_get_local_bus_nr(PCIE_BASE);
-}
-
static int pcie_valid_config(int bus, int dev)
{
/*
@@ -269,7 +264,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
*/
static DEFINE_SPINLOCK(orion5x_pci_lock);
-int orion5x_pci_local_bus_nr(void)
+static int orion5x_pci_local_bus_nr(void)
{
u32 conf = orion5x_read(PCI_P2P_CONF);
return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
@@ -557,3 +552,16 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys
return bus;
}
+
+int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int bus = dev->bus->number;
+
+ /*
+ * PCIe endpoint?
+ */
+ if (bus < orion5x_pci_local_bus_nr())
+ return IRQ_ORION5X_PCIE0_INT;
+
+ return -1;
+}