diff options
| author | Eric Miao <eric.miao@marvell.com> | 2009-01-02 23:17:22 +0800 |
|---|---|---|
| committer | Eric Miao <eric.miao@marvell.com> | 2009-03-09 21:22:36 +0800 |
| commit | 51c62982a33d9086fd8876293411d28a5f97247a (patch) | |
| tree | c3f0dd5cb7dfd20c17d307c7a7ab851217cef5ee /arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | |
| parent | 5b079b5ab4cfc6d23312b3bb0203f527bb1f79d0 (diff) | |
[ARM] pxa: introduce pxa{25x,27x,300,320,930}.h for board usage
Considering the header mess ATM, it is not always possible to include
the correct header files within board code. Let's keep this simple:
<mach/pxa25x.h> - for pxa25x based platforms
<mach/pxa27x.h> - for pxa27x based platforms
<mach/pxa300.h> - for pxa300 based platforms
<mach/pxa320.h> - for pxa320 based platforms
<mach/pxa930.h> - for pxa930 based platforms
NOTE:
1. one header one board file, they are not compatible (i.e. they have
conflicting definitions which won't compile if included together).
2. Unless strictly necessary, the following header files are considered
to be SoC files use _only_, and is not recommended to be included in
board code:
<mach/hardware.h>
<mach/pxa-regs.h>
<mach/pxa2xx-regs.h>
<mach/pxa3xx-regs.h>
<mach/mfp.h>
<mach/mfp-pxa2xx.h>
<mach/mfp-pxa25x.h>
<mach/mfp-pxa27x.h>
<mach/mfp-pxa3xx.h>
<mach/mfp-pxa300.h>
<mach/mfp-pxa320.h>
<mach/mfp-pxa930.h>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Diffstat (limited to 'arch/arm/mach-pxa/include/mach/pxa2xx-regs.h')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 77102d695cc..0b4ffd05a39 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -14,6 +14,8 @@ #ifndef __PXA2XX_REGS_H #define __PXA2XX_REGS_H +#include <mach/pxa-regs.h> + /* * Memory controller */ @@ -69,24 +71,6 @@ #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - -#ifdef CONFIG_PXA27x - -#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ - -#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ -#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ -#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ -#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ -#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ -#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ -#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ -#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ -#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ - -#endif - - /* * Power Manager */ |