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authorKukjin Kim <kgene.kim@samsung.com>2011-10-04 20:18:36 +0900
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 20:18:36 +0900
commitdb3c94a7edc6b29f8d52ba5884dec6a15feeadad (patch)
treeac9207a44cecafb9104ca4e1f46aecb9fe01383d /arch/arm/mach-s3c2416/clock.c
parentc9477f38cba225870862fd9e08868ae3d4abdfe0 (diff)
parent568f0e278c6dd33dc11bd19c4ad781d1f8d86800 (diff)
Merge branch 'next-samsung-devel' into next-samsung-devel-2
Conflicts: arch/arm/mach-exynos4/clock.c arch/arm/mach-s3c2412/gpio.c arch/arm/mach-s5p64x0/dma.c arch/arm/mach-s5p64x0/gpiolib.c
Diffstat (limited to 'arch/arm/mach-s3c2416/clock.c')
-rw-r--r--arch/arm/mach-s3c2416/clock.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 21a5e81f0ab..196fb37f4b1 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -38,6 +38,32 @@ static unsigned int armdiv[8] = {
[7] = 8,
};
+static struct clksrc_clk hsspi_eplldiv = {
+ .clk = {
+ .name = "hsspi-eplldiv",
+ .parent = &clk_esysclk.clk,
+ .ctrlbit = (1 << 14),
+ .enable = s3c2443_clkcon_enable_s,
+ },
+ .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
+};
+
+static struct clk *hsspi_sources[] = {
+ [0] = &hsspi_eplldiv.clk,
+ [1] = NULL, /* to fix */
+};
+
+static struct clksrc_clk hsspi_mux = {
+ .clk = {
+ .name = "hsspi-if",
+ },
+ .sources = &(struct clksrc_sources) {
+ .sources = hsspi_sources,
+ .nr_sources = ARRAY_SIZE(hsspi_sources),
+ },
+ .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
+};
+
static struct clksrc_clk hsmmc_div[] = {
[0] = {
.clk = {
@@ -114,6 +140,8 @@ void __init_or_cpufreq s3c2416_setup_clocks(void)
static struct clksrc_clk *clksrcs[] __initdata = {
+ &hsspi_eplldiv,
+ &hsspi_mux,
&hsmmc_div[0],
&hsmmc_div[1],
&hsmmc_mux[0],