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authorMark Brown <broonie@opensource.wolfsonmicro.com>2012-01-12 10:41:35 +0900
committerKukjin Kim <kgene.kim@samsung.com>2012-02-11 08:02:30 +0900
commited8d8aa1e674b5b03fceae56a81cccbcf60ec95e (patch)
tree9fdbdefdb6fb4882ce7f0c57f0dc89c7ff8e4c5f /arch/arm/mach-s3c64xx/clock.c
parent2abf13c9ffdcde537fc54b83f1bcd50cc758beca (diff)
ARM: S3C64XX: Gate some more clocks by default
Gate the AC'97 and CF clocks by default. The drivers will enable them required. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c64xx/clock.c')
-rw-r--r--arch/arm/mach-s3c64xx/clock.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 31bb27dc4ae..b58274f80cf 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -202,6 +202,15 @@ static struct clk init_clocks_off[] = {
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
}, {
+ .name = "ac97",
+ .parent = &clk_p,
+ .ctrlbit = S3C_CLKCON_PCLK_AC97,
+ }, {
+ .name = "cfcon",
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_IHOST,
+ }, {
.name = "dma0",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
@@ -284,16 +293,7 @@ static struct clk init_clocks[] = {
.name = "watchdog",
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT,
- }, {
- .name = "ac97",
- .parent = &clk_p,
- .ctrlbit = S3C_CLKCON_PCLK_AC97,
- }, {
- .name = "cfcon",
- .parent = &clk_h,
- .enable = s3c64xx_hclk_ctrl,
- .ctrlbit = S3C_CLKCON_HCLK_IHOST,
- }
+ },
};
static struct clk clk_hsmmc0 = {