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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-08-16 18:42:58 +0100
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-08-16 18:42:58 +0100
commite4862f2f6f5653dfb67f3ba2b6f0bc74516ed51a (patch)
tree1db5a0540a4eecfad9b7daee476b985e82ddc810 /arch/arm/mach-s3c64xx/setup-ide.c
parentec62dbd7eb8e3dddb221da89ecbcea0fc3dee8c1 (diff)
parentb2c1e07b81a126e5846dfc3d36f559d861df59f4 (diff)
Merge branch 'for-2.6.36' into for-2.6.37
Fairly simple conflicts, the most serious ones are the i.MX ones which I suspect now need another rename. Conflicts: arch/arm/mach-mx2/clock_imx27.c arch/arm/mach-mx2/devices.c arch/arm/mach-omap2/board-rx51-peripherals.c arch/arm/mach-omap2/board-zoom2.c sound/soc/fsl/mpc5200_dma.c sound/soc/fsl/mpc5200_dma.h sound/soc/fsl/mpc8610_hpcd.c sound/soc/pxa/spitz.c
Diffstat (limited to 'arch/arm/mach-s3c64xx/setup-ide.c')
-rw-r--r--arch/arm/mach-s3c64xx/setup-ide.c46
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c
new file mode 100644
index 00000000000..c12c315f33b
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-ide.c
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-s3c64xx/setup-ide.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S3C64XX setup information for IDE
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/gpio-cfg.h>
+
+void s3c64xx_ide_setup_gpio(void)
+{
+ u32 reg;
+ u32 gpio = 0;
+
+ reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
+
+ /* Independent CF interface, CF chip select configuration */
+ writel(reg | MEM_SYS_CFG_INDEP_CF |
+ MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
+
+ s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
+
+ /* Set XhiDATA[15:0] pins as CF Data[15:0] */
+ for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++)
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
+
+ /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
+ for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++)
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
+
+ /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
+ s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
+ for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++)
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
+}