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authorWill Deacon <will.deacon@arm.com>2010-09-27 14:55:15 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-09-27 14:57:36 +0100
commit2de59fea8b3095d1df4c729fda041625930aab4f (patch)
treeb7d5e28e4da11607c74a7ed99c3bd2f93473a8fd /arch/arm/mach-s5p6442
parent2de5c00ac06c8983ab33ad51a8341584f1cf42c3 (diff)
ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tile
The PL310 on the ct-ca9x4 tile for the Versatile Express does not need to add additional latency when accessing its cache RAMs. Unfortunately, the boot monitor sets this up for an 8-cycle delay on reads and writes, resulting in greatly reduced memory performance when the L2 cache is enabled. This patch sets the L2 RAM latencies to the correct value of 1 cycle on the ct-ca9x4 tile before enabling the L2 cache. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s5p6442')
0 files changed, 0 insertions, 0 deletions