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authorJaecheol Lee <jc.lee@samsung.com>2010-10-12 09:19:26 +0900
committerKukjin Kim <kgene.kim@samsung.com>2010-10-25 16:03:48 +0900
commit88695843973d3d53a087fc03049668600e91b5c4 (patch)
tree6598a2cbfb82d69110d0bda23c1d79e477f6ce41 /arch/arm/mach-s5pv210
parentb7a9825553e9213e5129f7e8e53065e918981a70 (diff)
ARM: S5PV210: Add struct clk_ops for clk_fout_apll
Current fout_apll has fixed rate value. So CPUFREQ driver gets incorrect value when finding current CPU frequency. Because some operation level need to change APLL. Added get_rate function for fout_apll can give correct frequency value when calling get_rate function. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r--arch/arm/mach-s5pv210/clock.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index d562670e1b0..e18e0980905 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -31,6 +31,8 @@
#include <plat/clock-clksrc.h>
#include <plat/s5pv210.h>
+static unsigned long xtal;
+
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
@@ -268,6 +270,15 @@ static struct clk_ops clk_hclk_imem_ops = {
.get_rate = s5pv210_clk_imem_get_rate,
};
+static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
+{
+ return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
+}
+
+static struct clk_ops clk_fout_apll_ops = {
+ .get_rate = s5pv210_clk_fout_apll_get_rate,
+};
+
static struct clk init_clocks_disable[] = {
{
.name = "rot",
@@ -958,7 +969,6 @@ static struct clksrc_clk *sysclks[] = {
void __init_or_cpufreq s5pv210_setup_clocks(void)
{
struct clk *xtal_clk;
- unsigned long xtal;
unsigned long vpllsrc;
unsigned long armclk;
unsigned long hclk_msys;
@@ -996,7 +1006,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
- clk_fout_apll.rate = apll;
+ clk_fout_apll.ops = &clk_fout_apll_ops;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_vpll.rate = vpll;