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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-12-04 16:13:29 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-14 19:21:42 +0000
commitff2e27ae0b17f53a6a289c87d325f706598f3788 (patch)
tree1288f491bce11b3d8a6d48604fd00d68bea6eb98 /arch/arm/mach-s5pv310/include
parent384895330e0f3954d9478fd0853145f9c169df12 (diff)
ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s5pv310/include')
-rw-r--r--arch/arm/mach-s5pv310/include/mach/smp.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index b7ec252384f..e1cc6a251c6 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -9,8 +9,6 @@
#include <asm/hardware/gic.h>
#include <asm/smp_mpidr.h>
-extern void __iomem *gic_cpu_base_addr;
-
/*
* We use IRQ1 as the IPI
*/