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authorMarcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>2010-12-16 21:34:51 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-21 14:53:46 +0000
commitb080ac8ad47aeeb845d8d11924f09255cf49b5e9 (patch)
treef42dcdbbdf725b798a20137fd8af0c10ab8d07bc /arch/arm/mach-sa1100/include
parentfa87672ab30ce6564393778b8cbc67fc32712a30 (diff)
ARM: 6459/2: sa1100: Add nanoEngine PCI support.
This patch adds nanoEngine's PCI support. Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-sa1100/include')
-rw-r--r--arch/arm/mach-sa1100/include/mach/hardware.h8
-rw-r--r--arch/arm/mach-sa1100/include/mach/nanoengine.h22
2 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 99f5856d8de..967ae768439 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -76,4 +76,12 @@ static inline unsigned long get_clock_tick_rate(void)
#include "SA-1101.h"
#endif
+#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI)
+#define PCIBIOS_MIN_IO 0
+#define PCIBIOS_MIN_MEM 0
+#define pcibios_assign_all_busses() 1
+#define HAVE_ARCH_PCI_SET_DMA_MASK 1
+#endif
+
+
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
index 05377664552..14f8382d066 100644
--- a/arch/arm/mach-sa1100/include/mach/nanoengine.h
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -14,6 +14,8 @@
#ifndef __ASM_ARCH_NANOENGINE_H
#define __ASM_ARCH_NANOENGINE_H
+#include <mach/irqs.h>
+
#define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/
#define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */
#define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */
@@ -21,10 +23,30 @@
#define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */
#define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */
+#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0
#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11
#define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12
#define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13
#define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14
+/*
+ * nanoEngine Memory Map:
+ *
+ * 0000.0000 - 003F.0000 - 4 MB Flash
+ * C000.0000 - C1FF.FFFF - 32 MB SDRAM
+ * 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write
+ * 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space
+ * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
+ * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
+ *
+ */
+
+#define NANO_PCI_MEM_RW_PHYS 0x18600000
+#define NANO_PCI_MEM_RW_VIRT 0xf1000000
+#define NANO_PCI_MEM_RW_SIZE SZ_1M
+#define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000
+#define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000
+#define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K
+
#endif