diff options
| author | Rafael J. Wysocki <rjw@sisk.pl> | 2012-07-11 23:02:05 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki <rjw@sisk.pl> | 2012-07-11 23:02:05 +0200 |
| commit | b0a1e7532b69e07ab64db622d9d998af0a6e2f97 (patch) | |
| tree | b13b7799d3ac6dd8cb63c9f7fc627a5c4e297e61 /arch/arm/mach-shmobile/pfc-r8a7740.c | |
| parent | 992c91eeca5fc7249de6afbba49064640f620d4a (diff) | |
| parent | 755d57b2229bd8cfa1d553c0b6878f2096f55ec3 (diff) | |
Merge branch 'renesas-r8a7740' into renesas-soc
* renesas-r8a7740:
ARM: mach-shmobile: r8a7740 generic board support via DT
ARM: shmobile: r8a7740: add A4LC pm domain support
ARM: shmobile: r8a7740: add A3SP pm domain support
ARM: shmobile: r8a7740: add A4S pm domain support
ARM: shmobile: r8a7740: fixup: MSEL1CR 7bit control
ARM: shmobile: use common DMAEngine definitions on r8a7740
ARM: shmobile: r8a7740: add DMAEngine support for USB
ARM: shmobile: r8a7740: add DMAEngine support for SDHI
ARM: shmobile: r8a7740: add DMAEngine support for FSI
Diffstat (limited to 'arch/arm/mach-shmobile/pfc-r8a7740.c')
| -rw-r--r-- | arch/arm/mach-shmobile/pfc-r8a7740.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c index 03def0fd7a0..ce9e7fa5cc8 100644 --- a/arch/arm/mach-shmobile/pfc-r8a7740.c +++ b/arch/arm/mach-shmobile/pfc-r8a7740.c @@ -1261,7 +1261,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(A21_MARK, PORT120_FN1), PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2), PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0), - PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0), + PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1), /* Port121 */ PINMUX_DATA(A20_MARK, PORT121_FN1), @@ -1623,7 +1623,7 @@ static pinmux_enum_t pinmux_data[] = { /* Port209 */ PINMUX_DATA(VBUS_MARK, PORT209_FN1), - PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1), + PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0), /* Port210 */ PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1), |