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| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2012-05-09 20:38:35 +0530 |
|---|---|---|
| committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2012-07-09 19:14:39 +0530 |
| commit | 247c445c0fbd52c77e497ff5bfcf0dceb8afea8d (patch) | |
| tree | 3334a9cd1b573fa5d447cf0876e8904d21aef105 /arch/arm/mach-spear6xx | |
| parent | e17933c2c0173ec19aa2450e4be79b7adfd52224 (diff) | |
ARM: OMAP5: Add the WakeupGen IP updates
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.
Patch updates the WakeupGen code accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-spear6xx')
0 files changed, 0 insertions, 0 deletions