diff options
| author | Olof Johansson <olof@lixom.net> | 2012-12-15 22:20:58 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-12-17 10:04:27 -0800 |
| commit | 0f600f40d752fe1f47aca29b8b95140283beda6b (patch) | |
| tree | 4f5b82a1172506970324bb20fe6d8dd23570fe89 /arch/arm/mach-tegra | |
| parent | 6a2461a49dad961c1a7feea6617bf8252826ee3f (diff) | |
| parent | f110174910896b7a7d91c0c60d19136815f68c54 (diff) | |
Merge tag 'tegra-for-3.8-fixes-for-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into fixes
ARM: tegra: fixes for 3.8
This branch contains a few miscellaneous fixes that have shown up in the
last few weeks.
By Sivaram Nair (2) and Hiroshi Doyu (1)
via Stephen Warren
* tag 'tegra-for-3.8-fixes-for-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
amba: tegra-ahb: Fix warning w/o PM_SLEEP
ARM: tegra: fix comment in dsib clk set_parent
ARM: tegra: select correct parent clk for pll_p
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra30_clocks.c | 4 |
2 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 0816562725f..d54cfc54b9f 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -104,7 +104,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, - { "pll_p", "clk_m", 408000000, true }, + { "pll_p", "pll_ref", 408000000, true }, { "pll_p_out1", "pll_p", 9600000, true }, { "pll_p_out4", "pll_p", 102000000, true }, { "sclk", "pll_p_out4", 102000000, true }, diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index efc000e32e1..d7147779f8e 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -2045,9 +2045,7 @@ struct clk_ops tegra30_periph_clk_ops = { static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index) { struct clk *d = clk_get_sys(NULL, "pll_d"); - /* The DSIB parent selection bit is in PLLD base - register - can not do direct r-m-w, must be - protected by PLLD lock */ + /* The DSIB parent selection bit is in PLLD base register */ tegra_clk_cfg_ex( d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index); |