diff options
author | Pawel Moll <pawel.moll@arm.com> | 2012-06-12 16:14:03 +0100 |
---|---|---|
committer | Pawel Moll <pawel.moll@arm.com> | 2012-07-12 16:16:56 +0100 |
commit | d927daf5c81c9b6bf2d6a83dc4c8c60268930ee5 (patch) | |
tree | e0a45cf8833d54d2b811b1b5a9635b3b8c844084 /arch/arm/mach-vexpress/v2m.c | |
parent | ef5911966d2312478a74e93d993cd623a869ab10 (diff) |
ARM: vexpress: Check master site in daughterboard's sysctl operations
With recent enough motherboard firmware, core tile can be fitted
in either of the two daughterboard sites. The non-DT tile code for
V2P-CA9 did not check that when configuring DVI output nor setting
CLCD pixel clock.
Fixed now, providing "get master site" API in motherboard's code.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Diffstat (limited to 'arch/arm/mach-vexpress/v2m.c')
-rw-r--r-- | arch/arm/mach-vexpress/v2m.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index fde26adaef3..bb185921fce 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -147,6 +147,13 @@ void __init v2m_flags_set(u32 data) writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET); } +int v2m_get_master_site(void) +{ + u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC); + + return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1; +} + static struct resource v2m_pcie_i2c_resource = { .start = V2M_SERIAL_BUS_PCI, @@ -326,7 +333,8 @@ static long v2m_osc_round(struct clk *clk, unsigned long rate) static int v2m_osc1_set(struct clk *clk, unsigned long rate) { - return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate); + return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(SYS_CFG_SITE_MB) | 1, + rate); } static const struct clk_ops osc1_clk_ops = { @@ -404,13 +412,13 @@ static void __init v2m_init_early(void) static void v2m_power_off(void) { - if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0)) + if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0)) printk(KERN_EMERG "Unable to shutdown\n"); } static void v2m_restart(char str, const char *cmd) { - if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) + if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0)) printk(KERN_EMERG "Unable to reboot\n"); } @@ -605,8 +613,8 @@ void __init v2m_dt_init_early(void) /* Confirm board type against DT property, if available */ if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) { - u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC); - u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ? + int site = v2m_get_master_site(); + u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ? V2M_SYS_PROCID1 : V2M_SYS_PROCID0)); u32 hbi = id & SYS_PROCIDx_HBI_MASK; |