diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2008-04-21 18:42:04 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-24 10:06:45 +0100 |
| commit | 4a1fd556c1f1fbd6d9d6739efec042324732b697 (patch) | |
| tree | 0175c078b97e3e74249a07df619280832fa06b37 /arch/arm/mm/Kconfig | |
| parent | 328d8a012583f0c25f8db25a2e5e63b521201542 (diff) | |
[ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f
The proc-*.S files have the _prefetch_abort pointer placed at the end
of the processor structure but the cpu-multi32.h defines it in the
second position. The patch also fixes the support for XSC3 and the
MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/Kconfig')
| -rw-r--r-- | arch/arm/mm/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 746cbb7c8e9..1b8229d9c9d 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -32,6 +32,7 @@ config CPU_ARM7TDMI depends on !MMU select CPU_32v4T select CPU_ABRT_LV4T + select CPU_PABRT_NOIFAR select CPU_CACHE_V4 help A 32-bit RISC microprocessor based on the ARM7 processor core @@ -85,6 +86,7 @@ config CPU_ARM740T depends on !MMU select CPU_32v4T select CPU_ABRT_LV4T + select CPU_PABRT_NOIFAR select CPU_CACHE_V3 # although the core is v4t select CPU_CP15_MPU help @@ -101,6 +103,7 @@ config CPU_ARM9TDMI depends on !MMU select CPU_32v4T select CPU_ABRT_NOMMU + select CPU_PABRT_NOIFAR select CPU_CACHE_V4 help A 32-bit RISC microprocessor based on the ARM9 processor core @@ -200,6 +203,7 @@ config CPU_ARM940T depends on !MMU select CPU_32v4T select CPU_ABRT_NOMMU + select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MPU help @@ -217,6 +221,7 @@ config CPU_ARM946E depends on !MMU select CPU_32v5 select CPU_ABRT_NOMMU + select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MPU help @@ -351,6 +356,7 @@ config CPU_XSC3 default y select CPU_32v5 select CPU_ABRT_EV5T + select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_TLB_V4WBI if MMU |