diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-06-26 14:35:07 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-07-02 10:56:11 +0100 |
| commit | 3e287bec6fde088bff05ee7f998f53e8ac75b922 (patch) | |
| tree | 4ad814de273327ae1e6ddc354ab0ab6bb9653246 /arch/arm/mm/abort-ev6.S | |
| parent | 8dfe7ac96fedd4f5219879f63a8a546a33609daf (diff) | |
ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5
Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather
than r2/r3.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/abort-ev6.S')
| -rw-r--r-- | arch/arm/mm/abort-ev6.S | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index ef526e702a5..52db4a3fc5f 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -4,8 +4,8 @@ /* * Function: v6_early_abort * - * Params : r2 = address of aborted instruction - * : r3 = saved SPSR + * Params : r4 = aborted context pc + * : r5 = aborted context psr * * Returns : r0 = address of abort * : r1 = FSR, bit 11 = write @@ -33,10 +33,10 @@ ENTRY(v6_early_abort) * The test below covers all the write situations, including Java bytecodes */ bic r1, r1, #1 << 11 @ clear bit 11 of FSR - tst r3, #PSR_J_BIT @ Java? + tst r5, #PSR_J_BIT @ Java? movne pc, lr - do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3 - ldreq r3, [r2] @ read aborted ARM instruction + do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 + ldreq r3, [r4] @ read aborted ARM instruction #ifdef CONFIG_CPU_ENDIAN_BE8 reveq r3, r3 #endif @@ -44,5 +44,3 @@ ENTRY(v6_early_abort) tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. mov pc, lr - - |